From patchwork Thu Aug 4 10:36:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Volodymyr Fialko X-Patchwork-Id: 114612 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A94AA00C4; Thu, 4 Aug 2022 12:37:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D9FAA42BFA; Thu, 4 Aug 2022 12:37:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7DF1142BF2 for ; Thu, 4 Aug 2022 12:36:59 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2748BrPM012709; Thu, 4 Aug 2022 03:36:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=fyHsl5FFPF1D7z+fj/Oq2XNA1t1dVn90ryXXH8xGkxw=; b=i0AyPnXF1uMsqnu2gbWjGRGs202gVlOx4KUzAloIwy40DGiDExNgCWWlAwAMaGsTRo85 3xpK45to/BcszQt/AKG+yYjZ3YZCFRViukAcrPVqNF4tzzbs5fgSELyFK5uqmMlqfnt6 gu8KruJ/NTzam1NgOUvcQALNdM3yIw6P0XZzfPry1M7ZKCRr/q/tlHwt//6fxde+82XN sL77bXwqV5MdALIePx0YnJJpRui6fyz+FYoDK1BJVEPjTXFKa68KqOkowQZArv6MMqbY VJh590O/XyZoRFFzkhZbY1OeMGGGT8WnRbmZgGGiM/kxnYX3uPZlVlRNCnTuhS3ZsWpi iA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3hqp04n618-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 03:36:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Aug 2022 03:36:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 4 Aug 2022 03:36:57 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 5A6653F705C; Thu, 4 Aug 2022 03:36:55 -0700 (PDT) From: Volodymyr Fialko To: , Radu Nicolau , Akhil Goyal CC: , , Volodymyr Fialko Subject: [PATCH 6/6] examples/ipsec-secgw: reduce number of QP for event lookaside Date: Thu, 4 Aug 2022 12:36:26 +0200 Message-ID: <20220804103626.102688-7-vfialko@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220804103626.102688-1-vfialko@marvell.com> References: <20220804103626.102688-1-vfialko@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: XGJPwk0KqPXv5EHsHMrfCuv5Bli3MgrE X-Proofpoint-ORIG-GUID: XGJPwk0KqPXv5EHsHMrfCuv5Bli3MgrE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-04_03,2022-08-04_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Limit number of queue pairs to one for event lookaside mode, since all cores are using same queue in this mode. Signed-off-by: Volodymyr Fialko --- examples/ipsec-secgw/ipsec-secgw.c | 67 +++++++++++++++++------------- 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c index 02b1fabaf5..d6b5b73811 100644 --- a/examples/ipsec-secgw/ipsec-secgw.c +++ b/examples/ipsec-secgw/ipsec-secgw.c @@ -1541,7 +1541,7 @@ add_mapping(const char *str, uint16_t cdev_id, } static int32_t -add_cdev_mapping(struct rte_cryptodev_info *dev_info, uint16_t cdev_id, +add_cdev_mapping(const struct rte_cryptodev_info *dev_info, uint16_t cdev_id, uint16_t qp, struct lcore_params *params) { int32_t ret = 0; @@ -1597,6 +1597,37 @@ add_cdev_mapping(struct rte_cryptodev_info *dev_info, uint16_t cdev_id, return ret; } +static uint16_t +map_cdev_to_cores_from_config(enum eh_pkt_transfer_mode mode, int16_t cdev_id, + const struct rte_cryptodev_info *cdev_info, + uint16_t *last_used_lcore_id) +{ + uint16_t nb_qp = 0, i = 0, max_nb_qps; + + /* For event lookaside mode all sessions are bound to single qp. + * It's enough to bind one core, since all cores will share same qp + * Event inline mode do not use this functionality. + */ + if (mode == EH_PKT_TRANSFER_MODE_EVENT) { + add_cdev_mapping(cdev_info, cdev_id, nb_qp, &lcore_params[0]); + return 1; + } + + /* Check if there are enough queue pairs for all configured cores */ + max_nb_qps = RTE_MIN(nb_lcore_params, cdev_info->max_nb_queue_pairs); + + while (nb_qp < max_nb_qps && i < nb_lcore_params) { + if (add_cdev_mapping(cdev_info, cdev_id, nb_qp, + &lcore_params[*last_used_lcore_id])) + nb_qp++; + (*last_used_lcore_id)++; + *last_used_lcore_id %= nb_lcore_params; + i++; + } + + return nb_qp; +} + /* Check if the device is enabled by cryptodev_mask */ static int check_cryptodev_mask(uint8_t cdev_id) @@ -1608,13 +1639,13 @@ check_cryptodev_mask(uint8_t cdev_id) } static uint16_t -cryptodevs_init(uint16_t req_queue_num) +cryptodevs_init(enum eh_pkt_transfer_mode mode) { + struct rte_hash_parameters params = { 0 }; struct rte_cryptodev_config dev_conf; struct rte_cryptodev_qp_conf qp_conf; - uint16_t idx, max_nb_qps, qp, total_nb_qps, i; + uint16_t idx, qp, total_nb_qps; int16_t cdev_id; - struct rte_hash_parameters params = { 0 }; const uint64_t mseg_flag = multi_seg_required() ? RTE_CRYPTODEV_FF_IN_PLACE_SGL : 0; @@ -1655,23 +1686,8 @@ cryptodevs_init(uint16_t req_queue_num) cdev_id, rte_cryptodev_get_feature_name(mseg_flag)); - if (nb_lcore_params > cdev_info.max_nb_queue_pairs) - max_nb_qps = cdev_info.max_nb_queue_pairs; - else - max_nb_qps = nb_lcore_params; - - qp = 0; - i = 0; - while (qp < max_nb_qps && i < nb_lcore_params) { - if (add_cdev_mapping(&cdev_info, cdev_id, qp, - &lcore_params[idx])) - qp++; - idx++; - idx = idx % nb_lcore_params; - i++; - } - qp = RTE_MIN(max_nb_qps, RTE_MAX(req_queue_num, qp)); + qp = map_cdev_to_cores_from_config(mode, cdev_id, &cdev_info, &idx); if (qp == 0) continue; @@ -2985,15 +3001,6 @@ main(int32_t argc, char **argv) sess_sz = max_session_size(); - /* - * In event mode request minimum number of crypto queues - * to be reserved equal to number of ports. - */ - if (eh_conf->mode == EH_PKT_TRANSFER_MODE_EVENT) - nb_crypto_qp = rte_eth_dev_count_avail(); - else - nb_crypto_qp = 0; - /* * In event lookaside mode request memory for crypto metadata. Should * be removed once API will no longer require usage of user data in @@ -3004,7 +3011,7 @@ main(int32_t argc, char **argv) else user_data_sz = 0; - nb_crypto_qp = cryptodevs_init(nb_crypto_qp); + nb_crypto_qp = cryptodevs_init(eh_conf->mode); if (nb_bufs_in_pool == 0) { RTE_ETH_FOREACH_DEV(portid) {