[08/10] net/gve: add support to get dev info and configure dev
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Commit Message
Add dev_ops dev_infos_get.
Complete dev_configure with RX offloads configuration.
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
---
drivers/net/gve/gve.h | 3 ++
drivers/net/gve/gve_ethdev.c | 61 ++++++++++++++++++++++++++++++++++++
2 files changed, 64 insertions(+)
@@ -27,6 +27,9 @@
#define GVE_DEFAULT_TX_FREE_THRESH 256
#define GVE_TX_MAX_FREE_SZ 512
+#define GVE_MIN_BUF_SIZE 1024
+#define GVE_MAX_RX_PKTLEN 65535
+
/* PTYPEs are always 10 bits. */
#define GVE_NUM_PTYPES 1024
@@ -96,6 +96,14 @@ gve_free_qpls(struct gve_priv *priv)
static int
gve_dev_configure(__rte_unused struct rte_eth_dev *dev)
{
+ struct gve_priv *priv = dev->data->dev_private;
+
+ if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
+ dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
+
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)
+ priv->enable_lsc = 1;
+
return 0;
}
@@ -266,6 +274,58 @@ gve_dev_close(struct rte_eth_dev *dev)
return err;
}
+static int
+gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
+{
+ struct gve_priv *priv = dev->data->dev_private;
+
+ dev_info->device = dev->device;
+ dev_info->max_mac_addrs = 1;
+ dev_info->max_rx_queues = priv->max_nb_rxq;
+ dev_info->max_tx_queues = priv->max_nb_txq;
+ dev_info->min_rx_bufsize = GVE_MIN_BUF_SIZE;
+ dev_info->max_rx_pktlen = GVE_MAX_RX_PKTLEN;
+
+ dev_info->rx_offload_capa = 0;
+ dev_info->tx_offload_capa =
+ RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
+ RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
+ RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
+ RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
+ RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
+ RTE_ETH_TX_OFFLOAD_TCP_TSO;
+
+ if (priv->queue_format == GVE_DQO_RDA_FORMAT)
+ dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO;
+
+ dev_info->default_rxconf = (struct rte_eth_rxconf) {
+ .rx_free_thresh = GVE_DEFAULT_RX_FREE_THRESH,
+ .rx_drop_en = 0,
+ .offloads = 0,
+ };
+
+ dev_info->default_txconf = (struct rte_eth_txconf) {
+ .tx_free_thresh = GVE_DEFAULT_TX_FREE_THRESH,
+ .offloads = 0,
+ };
+
+ dev_info->default_rxportconf.ring_size = priv->rx_desc_cnt;
+ dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
+ .nb_max = priv->rx_desc_cnt,
+ .nb_min = priv->rx_desc_cnt,
+ .nb_align = 1,
+ };
+
+ dev_info->default_txportconf.ring_size = priv->tx_desc_cnt;
+ dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
+ .nb_max = priv->tx_desc_cnt,
+ .nb_min = priv->tx_desc_cnt,
+ .nb_align = 1,
+ };
+
+ return 0;
+}
+
static int
gve_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
{
@@ -299,6 +359,7 @@ static const struct eth_dev_ops gve_eth_dev_ops = {
.dev_start = gve_dev_start,
.dev_stop = gve_dev_stop,
.dev_close = gve_dev_close,
+ .dev_infos_get = gve_dev_info_get,
.rx_queue_setup = gve_rx_queue_setup,
.tx_queue_setup = gve_tx_queue_setup,
.link_update = gve_link_update,