From patchwork Thu Jul 7 16:26:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 113779 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD89CA0540; Thu, 7 Jul 2022 10:29:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B4CC40A7B; Thu, 7 Jul 2022 10:29:00 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 66CAD406B4 for ; Thu, 7 Jul 2022 10:28:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657182539; x=1688718539; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ax4iU7arrLh3FsaTSNpYQ5pXogSTvV4WuKCDYraz1JY=; b=nnli8VREuFkHDBBzSxl86xtC808IRFBl803YdT2Hbav5XacnHJMtHd4K sN+5HvDpppLOWyw3MjWejnnaqUOf/XkieLAy8TP/lJR86lmsoe6AJe3JS Z32PGQDxiK+Yj0ZLw40qC3/q3v5sNhlYF08HOSStkkNtxoI2D6rifmcIG rWgU44oZiW4ZZCOcDe4HEkog20R/EqKnyaR7OuMKjNG5OB1qtGyGVIvja 6xS+0cRmEiImFUZW0x5j30b+tG3U4vyvLC37qtd/I4y1Rx5FNHm/jbyVu jEX4m4YLhNCMTL7bvMnoqvNyu2g2lQ84rDV8N4YkOSWKTnaUnT4qBMzBo g==; X-IronPort-AV: E=McAfee;i="6400,9594,10400"; a="281515099" X-IronPort-AV: E=Sophos;i="5.92,252,1650956400"; d="scan'208";a="281515099" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 01:28:43 -0700 X-IronPort-AV: E=Sophos;i="5.92,252,1650956400"; d="scan'208";a="620697189" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.191]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 01:28:40 -0700 From: Kevin Liu To: dev@dpdk.org Cc: beilei.xing@intel.com, Yuying.Zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH v3] net/i40e: restore disable double VLAN by default Date: Thu, 7 Jul 2022 16:26:02 +0000 Message-Id: <20220707162602.2123584-1-kevinx.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220707104732.1816933-1-kevinx.liu@intel.com> References: <20220707104732.1816933-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previously, QinQ is enabled by default and can't be disabled, but there'll be performance drop if QinQ is enabled. So, disable QinQ by default. Fixes: ae97b8b89826 ("net/i40e: fix error disable double VLAN") Signed-off-by: Kevin Liu --- v2: update doc and refine commit log --- v3: refine commit log --- doc/guides/nics/i40e.rst | 11 +++++++---- drivers/net/i40e/i40e_ethdev.c | 12 ------------ 2 files changed, 7 insertions(+), 16 deletions(-) diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index 85fdc4944d..75ff40aa59 100644 --- a/doc/guides/nics/i40e.rst +++ b/doc/guides/nics/i40e.rst @@ -969,11 +969,14 @@ it will fail and return the info "Conflict with the first rule's input set", which means the current rule's input set conflicts with the first rule's. Remove the first rule if want to change the input set of the PCTYPE. -Disable QinQ is not supported when FW >= 8.4 -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -If upgrade FW to version 8.4 and higher, enable QinQ by default and disable QinQ is not supported. +Vlan related feature miss when FW >= 8.4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +If upgrade FW to version 8.4 and higher, some vlan related issue exist: +1. vlan tci input set not work +2. tpid set fail +3. need enable qinq before use vlan filter +4. outer vlan strip fail Example of getting best performance with l3fwd example ------------------------------------------------------ diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 684e095026..117dd85c11 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -4027,12 +4027,6 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) } if (mask & RTE_ETH_VLAN_EXTEND_MASK) { - /* Double VLAN not allowed to be disabled.*/ - if (pf->fw8_3gt && !(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) { - PMD_DRV_LOG(WARNING, - "Disable double VLAN is not allowed after firmwarev8.3!"); - return 0; - } i = 0; num = vsi->mac_num; mac_filter = rte_zmalloc("mac_filter_info_data", @@ -6296,7 +6290,6 @@ int i40e_vsi_cfg_inner_vlan_stripping(struct i40e_vsi *vsi, bool on) static int i40e_dev_init_vlan(struct rte_eth_dev *dev) { - struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct rte_eth_dev_data *data = dev->data; int ret; int mask = 0; @@ -6307,11 +6300,6 @@ i40e_dev_init_vlan(struct rte_eth_dev *dev) RTE_ETH_VLAN_FILTER_MASK | RTE_ETH_VLAN_EXTEND_MASK; - /* Double VLAN be enabled by default.*/ - if (pf->fw8_3gt) { - struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; - rxmode->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; - } ret = i40e_vlan_offload_set(dev, mask); if (ret) { PMD_DRV_LOG(INFO, "Failed to update vlan offload");