diff mbox series

[RFC,09/29] net/qdma: define device modes and data structure

Message ID 20220706075219.517046-10-aman.kumar@vvdntech.in (mailing list archive)
State New
Delegated to: Thomas Monjalon
Headers show
Series cover letter for net/qdma PMD | expand

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Aman Kumar July 6, 2022, 7:51 a.m. UTC
define enums and structure for supported device modes
adapt macros into the routines.

Signed-off-by: Aman Kumar <aman.kumar@vvdntech.in>
---
 drivers/net/qdma/qdma.h         |  21 +++
 drivers/net/qdma/qdma_common.c  |  22 ++-
 drivers/net/qdma/qdma_ethdev.c  |  17 ++-
 drivers/net/qdma/rte_pmd_qdma.h | 262 ++++++++++++++++++++++++++++++++
 4 files changed, 316 insertions(+), 6 deletions(-)
 create mode 100644 drivers/net/qdma/rte_pmd_qdma.h
diff mbox series

Patch

diff --git a/drivers/net/qdma/qdma.h b/drivers/net/qdma/qdma.h
index db59cddd25..7c2d3b34e0 100644
--- a/drivers/net/qdma/qdma.h
+++ b/drivers/net/qdma/qdma.h
@@ -17,6 +17,7 @@ 
 #include <linux/pci.h>
 
 #include "qdma_resource_mgmt.h"
+#include "rte_pmd_qdma.h"
 #include "qdma_log.h"
 
 #define QDMA_NUM_BARS          (6)
@@ -28,6 +29,26 @@ 
 #define DEFAULT_QUEUE_BASE	(0)
 
 #define DEFAULT_TIMER_CNT_TRIG_MODE_TIMER	(5)
+#define DEFAULT_TIMER_CNT_TRIG_MODE_COUNT_TIMER	(30)
+
+/* Completion Context config */
+#define CMPT_DEFAULT_COLOR_BIT           (1)
+#define CMPT_CNTXT_DESC_SIZE_8B          (0)
+#define CMPT_CNTXT_DESC_SIZE_16B         (1)
+#define CMPT_CNTXT_DESC_SIZE_32B         (2)
+#define CMPT_CNTXT_DESC_SIZE_64B         (3)
+
+/* SOFTWARE DESC CONTEXT */
+#define SW_DESC_CNTXT_8B_BYPASS_DMA	    (0)
+#define SW_DESC_CNTXT_16B_BYPASS_DMA	    (1)
+#define SW_DESC_CNTXT_32B_BYPASS_DMA	    (2)
+#define SW_DESC_CNTXT_64B_BYPASS_DMA	    (3)
+
+#define SW_DESC_CNTXT_C2H_STREAM_DMA        (0)
+#define SW_DESC_CNTXT_H2C_STREAM_DMA        (1)
+#define SW_DESC_CNTXT_MEMORY_MAP_DMA        (2)
+
+#define DEFAULT_QDMA_CMPT_DESC_LEN (RTE_PMD_QDMA_CMPT_DESC_LEN_8B)
 
 enum dma_data_direction {
 	DMA_BIDIRECTIONAL = 0,
diff --git a/drivers/net/qdma/qdma_common.c b/drivers/net/qdma/qdma_common.c
index 0ea920f255..4f50be5b06 100644
--- a/drivers/net/qdma/qdma_common.c
+++ b/drivers/net/qdma/qdma_common.c
@@ -40,10 +40,11 @@  static int cmpt_desc_len_check_handler(__rte_unused const char *key,
 
 	PMD_DRV_LOG(INFO, "QDMA devargs cmpt_desc_len is: %s\n", value);
 	qdma_dev->cmpt_desc_len =  (uint8_t)strtoul(value, &end, 10);
-	if (qdma_dev->cmpt_desc_len != 8 &&
-		qdma_dev->cmpt_desc_len != 16 &&
-		qdma_dev->cmpt_desc_len != 32 &&
-		qdma_dev->cmpt_desc_len != 64) {
+	if (qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_8B &&
+	    qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_16B &&
+	    qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_32B &&
+	    (qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_64B ||
+	     !qdma_dev->dev_cap.cmpt_desc_64b)) {
 		PMD_DRV_LOG(INFO, "QDMA devargs incorrect cmpt_desc_len = %d "
 						  "specified\n",
 						  qdma_dev->cmpt_desc_len);
@@ -62,6 +63,12 @@  static int trigger_mode_handler(__rte_unused const char *key,
 	PMD_DRV_LOG(INFO, "QDMA devargs trigger mode: %s\n", value);
 	qdma_dev->trigger_mode =  (uint8_t)strtoul(value, &end, 10);
 
+	if (qdma_dev->trigger_mode >= RTE_PMD_QDMA_TRIG_MODE_MAX) {
+		qdma_dev->trigger_mode = RTE_PMD_QDMA_TRIG_MODE_MAX;
+		PMD_DRV_LOG(INFO, "QDMA devargs trigger mode invalid,"
+						  "reset to default: %d\n",
+						  qdma_dev->trigger_mode);
+	}
 	return 0;
 }
 
@@ -92,6 +99,13 @@  static int c2h_byp_mode_check_handler(__rte_unused const char *key,
 	PMD_DRV_LOG(INFO, "QDMA devargs c2h_byp_mode is: %s\n", value);
 	qdma_dev->c2h_bypass_mode =  (uint8_t)strtoul(value, &end, 10);
 
+	if (qdma_dev->c2h_bypass_mode >= RTE_PMD_QDMA_RX_BYPASS_MAX) {
+		PMD_DRV_LOG(INFO, "QDMA devargs incorrect "
+				"c2h_byp_mode= %d specified\n",
+						qdma_dev->c2h_bypass_mode);
+		return -1;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/net/qdma/qdma_ethdev.c b/drivers/net/qdma/qdma_ethdev.c
index bc902e607f..54776c637d 100644
--- a/drivers/net/qdma/qdma_ethdev.c
+++ b/drivers/net/qdma/qdma_ethdev.c
@@ -379,8 +379,8 @@  static int qdma_eth_dev_init(struct rte_eth_dev *dev)
 	dma_priv->timer_count = DEFAULT_TIMER_CNT_TRIG_MODE_TIMER;
 
 	dma_priv->en_desc_prefetch = 0; /* Keep prefetch default to 0 */
-	dma_priv->cmpt_desc_len = 0;
-	dma_priv->c2h_bypass_mode = 0;
+	dma_priv->cmpt_desc_len = DEFAULT_QDMA_CMPT_DESC_LEN;
+	dma_priv->c2h_bypass_mode = RTE_PMD_QDMA_RX_BYPASS_NONE;
 	dma_priv->h2c_bypass_mode = 0;
 
 	dma_priv->config_bar_idx = DEFAULT_PF_CONFIG_BAR;
@@ -439,6 +439,19 @@  static int qdma_eth_dev_init(struct rte_eth_dev *dev)
 	/* Getting the device attributes from the Hardware */
 	qdma_device_attributes_get(dev);
 
+	if (dma_priv->dev_cap.cmpt_trig_count_timer) {
+		/* Setting default Mode to
+		 * RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT
+		 */
+		dma_priv->trigger_mode =
+					RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT;
+	} else {
+		/* Setting default Mode to RTE_PMD_QDMA_TRIG_MODE_USER_TIMER */
+		dma_priv->trigger_mode = RTE_PMD_QDMA_TRIG_MODE_USER_TIMER;
+	}
+	if (dma_priv->trigger_mode == RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT)
+		dma_priv->timer_count = DEFAULT_TIMER_CNT_TRIG_MODE_COUNT_TIMER;
+
 	/* Create master resource node for queue management on the given
 	 * bus number. Node will be created only once per bus number.
 	 */
diff --git a/drivers/net/qdma/rte_pmd_qdma.h b/drivers/net/qdma/rte_pmd_qdma.h
new file mode 100644
index 0000000000..f5e3def613
--- /dev/null
+++ b/drivers/net/qdma/rte_pmd_qdma.h
@@ -0,0 +1,262 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017-2022 Xilinx, Inc. All rights reserved.
+ */
+
+#ifndef __RTE_PMD_QDMA_EXPORT_H__
+#define __RTE_PMD_QDMA_EXPORT_H__
+
+#include <rte_dev.h>
+#include <rte_ethdev.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_byteorder.h>
+#include <rte_memzone.h>
+#include <linux/pci.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup rte_pmd_qdma_enums Enumerations */
+/** @defgroup rte_pmd_qdma_struct Data Structures */
+/** @defgroup rte_pmd_qdma_func Functions */
+
+/**
+ * Bypass modes in C2H direction
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_rx_bypass_mode {
+	/** C2H bypass mode disabled */
+	RTE_PMD_QDMA_RX_BYPASS_NONE = 0,
+	/** C2H cache bypass mode */
+	RTE_PMD_QDMA_RX_BYPASS_CACHE = 1,
+	/** C2H simple bypass mode */
+	RTE_PMD_QDMA_RX_BYPASS_SIMPLE = 2,
+	/** C2H bypass mode invalid */
+	RTE_PMD_QDMA_RX_BYPASS_MAX
+};
+
+/**
+ * Bypass modes in H2C direction
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_tx_bypass_mode {
+	/** H2C bypass mode disabled */
+	RTE_PMD_QDMA_TX_BYPASS_NONE = 0,
+	/** H2C bypass mode enabled */
+	RTE_PMD_QDMA_TX_BYPASS_ENABLE = 1,
+	/** H2C bypass mode invalid */
+	RTE_PMD_QDMA_TX_BYPASS_MAX
+};
+
+/**
+ * Enum to specify the direction i.e. TX or RX
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_dir_type {
+	/** H2C direction */
+	RTE_PMD_QDMA_TX = 0,
+	/** C2H direction */
+	RTE_PMD_QDMA_RX,
+	/** Invalid Direction */
+	RTE_PMD_QDMA_DIR_TYPE_MAX
+};
+
+/**
+ * Enum to specify the PCIe function type i.e. PF or VF
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_pci_func_type {
+	/** Physical Function */
+	RTE_PMD_QDMA_PCI_FUNC_PF,
+	/** Virtual Function */
+	RTE_PMD_QDMA_PCI_FUNC_VF,
+	/** Invalid PCI Function */
+	RTE_PMD_QDMA_PCI_FUNC_TYPE_MAX,
+};
+
+/**
+ * Enum to specify the queue mode
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_queue_mode_t {
+	/** Memory mapped queue mode */
+	RTE_PMD_QDMA_MEMORY_MAPPED_MODE,
+	/** Streaming queue mode */
+	RTE_PMD_QDMA_STREAMING_MODE,
+	/** Invalid queue mode */
+	RTE_PMD_QDMA_QUEUE_MODE_MAX,
+};
+
+/**
+ * Enum to specify the completion trigger mode
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_tigger_mode_t {
+	/** Trigger mode disabled */
+	RTE_PMD_QDMA_TRIG_MODE_DISABLE,
+	/** Trigger mode every */
+	RTE_PMD_QDMA_TRIG_MODE_EVERY,
+	/** Trigger mode user count */
+	RTE_PMD_QDMA_TRIG_MODE_USER_COUNT,
+	/** Trigger mode user */
+	RTE_PMD_QDMA_TRIG_MODE_USER,
+	/** Trigger mode timer */
+	RTE_PMD_QDMA_TRIG_MODE_USER_TIMER,
+	/** Trigger mode timer + count */
+	RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT,
+	/** Trigger mode invalid */
+	RTE_PMD_QDMA_TRIG_MODE_MAX,
+};
+
+/**
+ * Enum to specify the completion descriptor length
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_cmpt_desc_len {
+	/** 8B Completion descriptor */
+	RTE_PMD_QDMA_CMPT_DESC_LEN_8B = 8,
+	/** 16B Completion descriptor */
+	RTE_PMD_QDMA_CMPT_DESC_LEN_16B = 16,
+	/** 32B Completion descriptor */
+	RTE_PMD_QDMA_CMPT_DESC_LEN_32B = 32,
+	/** 64B Completion descriptor */
+	RTE_PMD_QDMA_CMPT_DESC_LEN_64B = 64,
+	/** Invalid Completion descriptor */
+	RTE_PMD_QDMA_CMPT_DESC_LEN_MAX,
+};
+
+/**
+ * Enum to specify the bypass descriptor length
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_bypass_desc_len {
+	/** 8B Bypass descriptor */
+	RTE_PMD_QDMA_BYPASS_DESC_LEN_8B = 8,
+	/** 16B Bypass descriptor */
+	RTE_PMD_QDMA_BYPASS_DESC_LEN_16B = 16,
+	/** 32B Bypass descriptor */
+	RTE_PMD_QDMA_BYPASS_DESC_LEN_32B = 32,
+	/** 64B Bypass descriptor */
+	RTE_PMD_QDMA_BYPASS_DESC_LEN_64B = 64,
+	/** Invalid Bypass descriptor */
+	RTE_PMD_QDMA_BYPASS_DESC_LEN_MAX,
+};
+
+/**
+ * Enum to specify the debug request type
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_xdebug_type {
+	/** Debug Global registers */
+	RTE_PMD_QDMA_XDEBUG_QDMA_GLOBAL_CSR,
+	/** Debug Device specific structure */
+	RTE_PMD_QDMA_XDEBUG_QDMA_DEVICE_STRUCT,
+	/** Debug Queue information */
+	RTE_PMD_QDMA_XDEBUG_QUEUE_INFO,
+	/** Debug descriptor */
+	RTE_PMD_QDMA_XDEBUG_QUEUE_DESC_DUMP,
+	/** Invalid debug type */
+	RTE_PMD_QDMA_XDEBUG_MAX,
+};
+
+/**
+ * Enum to specify the queue ring for debug
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_xdebug_desc_type {
+	/** Debug C2H ring descriptor */
+	RTE_PMD_QDMA_XDEBUG_DESC_C2H,
+	/** Debug H2C ring descriptor */
+	RTE_PMD_QDMA_XDEBUG_DESC_H2C,
+	/** Debug CMPT ring descriptor */
+	RTE_PMD_QDMA_XDEBUG_DESC_CMPT,
+	/** Invalid debug type */
+	RTE_PMD_QDMA_XDEBUG_DESC_MAX,
+};
+
+/**
+ * Enum to specify the QDMA device type
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_device_type {
+	/** QDMA Soft device e.g. UltraScale+ IP's  */
+	RTE_PMD_QDMA_DEVICE_SOFT,
+	/** QDMA Versal device */
+	RTE_PMD_QDMA_DEVICE_VERSAL,
+	/** Invalid QDMA device  */
+	RTE_PMD_QDMA_DEVICE_NONE
+};
+
+/**
+ * Enum to specify the QDMA IP type
+ * @ingroup rte_pmd_qdma_enums
+ */
+enum rte_pmd_qdma_ip_type {
+	/** Versal Hard IP  */
+	RTE_PMD_QDMA_VERSAL_HARD_IP,
+	/** Versal Soft IP  */
+	RTE_PMD_QDMA_VERSAL_SOFT_IP,
+	/** QDMA Soft IP  */
+	RTE_PMD_QDMA_SOFT_IP,
+	/** EQDMA Soft IP  */
+	RTE_PMD_EQDMA_SOFT_IP,
+	/** Invalid IP type  */
+	RTE_PMD_QDMA_NONE_IP
+};
+
+/**
+ * Structure to hold the QDMA device attributes
+ *
+ * @ingroup rte_pmd_qdma_struct
+ */
+struct rte_pmd_qdma_dev_attributes {
+	/** Number of PFs*/
+	uint8_t num_pfs;
+	/** Number of Queues */
+	uint16_t num_qs;
+	/** Indicates whether FLR supported or not */
+	uint8_t flr_present:1;
+	/** Indicates whether ST mode supported or not */
+	uint8_t st_en:1;
+	/** Indicates whether MM mode supported or not */
+	uint8_t mm_en:1;
+	/** Indicates whether MM with Completions supported or not */
+	uint8_t mm_cmpt_en:1;
+	/** Indicates whether Mailbox supported or not */
+	uint8_t mailbox_en:1;
+	/** Debug mode is enabled/disabled for IP */
+	uint8_t debug_mode:1;
+	/** Descriptor Engine mode:
+	 * Internal only/Bypass only/Internal & Bypass
+	 */
+	uint8_t desc_eng_mode:2;
+	/** Number of MM channels */
+	uint8_t mm_channel_max;
+
+	/** To indicate support of
+	 * overflow check disable in CMPT ring
+	 */
+	uint8_t cmpt_ovf_chk_dis:1;
+	/** To indicate support of 64 bytes
+	 * C2H/H2C descriptor format
+	 */
+	uint8_t sw_desc_64b:1;
+	/** To indicate support of 64 bytes
+	 * CMPT descriptor format
+	 */
+	uint8_t cmpt_desc_64b:1;
+	/** To indicate support of
+	 * counter + timer trigger mode
+	 */
+	uint8_t cmpt_trig_count_timer:1;
+	/** Device Type */
+	enum rte_pmd_qdma_device_type device_type;
+	/** Versal IP Type */
+	enum rte_pmd_qdma_ip_type ip_type;
+};
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ifndef __RTE_PMD_QDMA_EXPORT_H__ */