From patchwork Thu Jun 16 07:07:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 112835 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B1EDA00C3; Thu, 16 Jun 2022 09:09:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 741494114F; Thu, 16 Jun 2022 09:09:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 23844410D0 for ; Thu, 16 Jun 2022 09:09:34 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25FN9p0S014305 for ; Thu, 16 Jun 2022 00:09:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=eX/ZTxEHEMqWw455hppitCPlO7CRkRJtKgdUKYdrLtU=; b=JqkNvMPsBVaZv9FMxZM7oJZYmehL/Hu700fGuN4qGkZSCsuN9MYL7/wBCKIvVvibQKYs 1Zu51YFPhRHPEw+kBqby8y0v5lPOEDwUk7JMtYBJsnNtrGP3+vjQBbEZNoSxz1ct7jqx BZDQYTVeI3MsmOGGO5cjzo7cgasw8+QOox6uc9xJvkF/VlmUX5MMG08bzIz/NSFU9YY9 IYjYpyzLXvceZKW5rdgMqZUhBSYuisj0tIhjeYLqBT7hw9Yi0W2XGT7YTLrif6ugTVhE OqdVIPbe7z3pJ0LsrodTz/rPDwd07e/kO75eMaTh5trqPpZEXe5axeC8KDwR4pudClg5 yw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gqruu9kg7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Jun 2022 00:09:34 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 16 Jun 2022 00:09:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 16 Jun 2022 00:09:32 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0668A3F703F; Thu, 16 Jun 2022 00:09:29 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , Shijith Thotton CC: Subject: [PATCH 01/12] common/cnxk: use computed value for wqe skip Date: Thu, 16 Jun 2022 12:37:32 +0530 Message-ID: <20220616070743.30658-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: y1eLYfu2HeB8wm_feZo8AS8Npz2WpDsy X-Proofpoint-GUID: y1eLYfu2HeB8wm_feZo8AS8Npz2WpDsy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use computed value for WQE skip instead of a hardcoded value. WQE skip needs to be number of 128B lines to accommodate rte_mbuf. Signed-off-by: Nithin Dabilpuram --- Depends-on: series=23500 ("common/cnxk: add cnf10kb support") drivers/common/cnxk/roc_nix_inl.h | 2 +- drivers/common/cnxk/roc_nix_inl_priv.h | 2 +- drivers/event/cnxk/cnxk_eventdev_adptr.c | 5 ++++- drivers/net/cnxk/cnxk_ethdev_sec.c | 5 ++++- 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index b1b4c5b..c7b1817 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -131,7 +131,7 @@ struct roc_nix_inl_dev { uint16_t channel; uint16_t chan_mask; bool attach_cptlf; - bool wqe_skip; + uint16_t wqe_skip; uint8_t spb_drop_pc; uint8_t lpb_drop_pc; bool set_soft_exp_poll; diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index d61c7b2..a775efc 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -84,7 +84,7 @@ struct nix_inl_dev { uint32_t ipsec_in_max_spi; uint32_t inb_spi_mask; bool attach_cptlf; - bool wqe_skip; + uint16_t wqe_skip; bool ts_ena; }; diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index fa96090..cf5b1dd 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -125,6 +125,7 @@ cnxk_sso_rxq_enable(struct cnxk_eth_dev *cnxk_eth_dev, uint16_t rq_id, { struct roc_nix *nix = &cnxk_eth_dev->nix; struct roc_nix_rq *rq; + uint16_t wqe_skip; int rc; rq = &cnxk_eth_dev->rqs[rq_id]; @@ -132,7 +133,9 @@ cnxk_sso_rxq_enable(struct cnxk_eth_dev *cnxk_eth_dev, uint16_t rq_id, rq->tt = ev->sched_type; rq->hwgrp = ev->queue_id; rq->flow_tag_width = 20; - rq->wqe_skip = 1; + wqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ); + wqe_skip = wqe_skip / ROC_CACHE_LINE_SZ; + rq->wqe_skip = wqe_skip; rq->tag_mask = (port_id & 0xF) << 20; rq->tag_mask |= (((port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV << 4)) << 24; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index d01ebb4..1de3454 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -264,6 +264,7 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv, char name[CNXK_NIX_INL_DEV_NAME_LEN]; struct roc_nix_inl_dev *inl_dev; const struct rte_memzone *mz; + uint16_t wqe_skip; int rc = -ENOMEM; RTE_SET_USED(pci_drv); @@ -295,7 +296,9 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv, inl_dev->attach_cptlf = true; /* WQE skip is one for DPDK */ - inl_dev->wqe_skip = true; + wqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ); + wqe_skip = wqe_skip / ROC_CACHE_LINE_SZ; + inl_dev->wqe_skip = wqe_skip; inl_dev->set_soft_exp_poll = true; rc = roc_nix_inl_dev_init(inl_dev); if (rc) {