diff mbox series

[09/10] common/cnxk: sync eth mode change command with firmware

Message ID 20220604162651.3503338-10-tduszynski@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series Sync BPHY changes |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tomasz Duszynski June 4, 2022, 4:26 p.m. UTC 
  Layout of eth mode change command defined by firmware has been changed
recently. So in order to retain compatibility between ROC and firmware
update existing codebase.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 11 +++++++--
 drivers/common/cnxk/roc_bphy_cgx.h      | 19 +++++++++++++-
 drivers/common/cnxk/roc_bphy_cgx_priv.h | 12 +++++----
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c   |  4 +++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h    | 33 +++++++++++++++++++++++++
 5 files changed, 71 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 4b62905164..a5df104088 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -367,8 +367,10 @@  roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 {
 	uint64_t scr1, scr0;
 
-	if (roc_model_is_cn10k())
+	if (roc_model_is_cn9k() &&
+	    (mode->use_portm_idx || mode->portm_idx || mode->mode_group_idx)) {
 		return -ENOTSUP;
+	}
 
 	if (!roc_cgx)
 		return -EINVAL;
@@ -383,7 +385,12 @@  roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
 	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
 	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
-	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX,
+			  mode->use_portm_idx) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX,
+			  mode->portm_idx) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX,
+			  mode->mode_group_idx) |
 	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
 
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 3b645eb130..4ce1316513 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -72,13 +72,30 @@  enum roc_bphy_cgx_eth_link_mode {
 	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
 	ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
 	ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT,
 	__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
 };
 
+enum roc_bphy_cgx_mode_group {
+	ROC_BPHY_CGX_MODE_GROUP_ETH,
+};
+
 struct roc_bphy_cgx_link_mode {
 	bool full_duplex;
 	bool an;
-	unsigned int port;
+	bool use_portm_idx;
+	unsigned int portm_idx;
+	enum roc_bphy_cgx_mode_group mode_group_idx;
 	enum roc_bphy_cgx_eth_link_speed speed;
 	enum roc_bphy_cgx_eth_link_mode mode;
 };
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index c8c406439c..78fa1eaa6b 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -74,11 +74,13 @@  enum eth_cmd_own {
 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
 
 /* struct eth_mode_change_args */
-#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED	 GENMASK_ULL(11, 8)
-#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
-#define SCR1_ETH_MODE_CHANGE_ARGS_AN	 BIT_ULL(13)
-#define SCR1_ETH_MODE_CHANGE_ARGS_PORT	 GENMASK_ULL(21, 14)
-#define SCR1_ETH_MODE_CHANGE_ARGS_MODE	 GENMASK_ULL(63, 22)
+#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED          GENMASK_ULL(11, 8)
+#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX         BIT_ULL(12)
+#define SCR1_ETH_MODE_CHANGE_ARGS_AN	         BIT_ULL(13)
+#define SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX  BIT_ULL(14)
+#define SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX      GENMASK_ULL(19, 15)
+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX GENMASK_ULL(21, 20)
+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE	         GENMASK_ULL(63, 22)
 
 /* struct eth_set_fec_args */
 #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index de1c372334..f839a70f04 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -112,6 +112,10 @@  cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
 		memset(&rlink_mode, 0, sizeof(rlink_mode));
 		rlink_mode.full_duplex = link_mode->full_duplex;
 		rlink_mode.an = link_mode->autoneg;
+		rlink_mode.use_portm_idx = link_mode->use_portm_idx;
+		rlink_mode.portm_idx = link_mode->portm_idx;
+		rlink_mode.mode_group_idx =
+			(enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx;
 		rlink_mode.speed =
 			(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
 		rlink_mode.mode =
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 86e58e4756..7f326e3643 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -143,14 +143,47 @@  enum cnxk_bphy_cgx_eth_link_mode {
 	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
 	/** 100GBASE-KR4 */
 	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	/** 50GAUI-2-C2C */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT,
+	/** 50GAUI-2-C2M */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT,
+	/** 50GBASE-CR2-C */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT,
+	/** 50GBASE-KR2-C */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT,
+	/** 100GAUI-2-C2C */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT,
+	/** 100GAUI-2-C2M */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT,
+	/** 100GBASE-CR2 */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT,
+	/** 100GBASE-KR2 */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT,
+	/** SFI-1G */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT,
+	/** 25GBASE-CR-C */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT,
+	/** 25GBASE-KR-C */
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT,
 	__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
 };
 
+enum cnxk_bphy_cgx_mode_group {
+	/** ETH group */
+	CNXK_BPHY_CGX_MODE_GROUP_ETH,
+};
+
 struct cnxk_bphy_cgx_msg_link_mode {
 	/** Setting for full-duplex */
 	bool full_duplex;
 	/** Setting for automatic link negotiation */
 	bool autoneg;
+	/** Set to true to use port index */
+	bool use_portm_idx;
+	/** Port index */
+	unsigned int portm_idx;
+	/** Mode group */
+	enum cnxk_bphy_cgx_mode_group mode_group_idx;
 	/** Link speed */
 	enum cnxk_bphy_cgx_eth_link_speed speed;
 	/** Link mode */