From patchwork Wed May 11 12:30:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 111029 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 560DFA0032; Wed, 11 May 2022 14:31:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B286742833; Wed, 11 May 2022 14:31:04 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 397944113D for ; Wed, 11 May 2022 14:31:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652272263; x=1683808263; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+hoKeWfHn+0Hm3MXG5iy/9y7LM0JdZCSeamIZOmiJYQ=; b=IvLyPN1aYfD2dWIc5ftEzKhpGPVnPApRWdkeDgrwRRE4huMUXYHxDWFj VPm8c8iLie1gu0x7vDe5zX/40euTuIT3c86bfB0vzVh1uqjfewCZv+H20 MmiHfaWxtEm3n42EZAx2xfQkLbkOW6Bm4AM5ZrW8ZtM0f/HHdAtDeZJzD f+BfPkfLNrXioh553GRkO7LhASCPE1Ya/By2LRtqCSho9eyuKHFVuo3EF uuefdgW2ECWWWdjT8k/9k156O3qUVtcsccsiYeivub2CuwjOaZSlin5v6 X/SJEMyj/BN5B0jgwU5PYpRMMqOX1ibZQAEPFrNYdOU0KsYbxIMtzBAVj w==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="294922353" X-IronPort-AV: E=Sophos;i="5.91,217,1647327600"; d="scan'208";a="294922353" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 05:31:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,217,1647327600"; d="scan'208";a="566157940" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.49]) by orsmga007.jf.intel.com with ESMTP; 11 May 2022 05:31:01 -0700 From: Ciara Power To: dev@dpdk.org Cc: roy.fan.zhang@intel.com, kai.ji@intel.com, pablo.de.lara.guarch@intel.com, Ciara Power Subject: [PATCH v2 2/2] crypto/ipsec_mb: add chachapoly SGL support to aesni-mb Date: Wed, 11 May 2022 12:30:45 +0000 Message-Id: <20220511123045.1154799-3-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220511123045.1154799-1-ciara.power@intel.com> References: <20220407103041.4037942-1-ciara.power@intel.com> <20220511123045.1154799-1-ciara.power@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add SGL support for chacha20_poly1305 algorithm through JOB API. Supports IN-PLACE SGL, OOP SGL IN and LB OUT, and OOP SGL IN and SGL OUT. Feature flags not added, as the PMD does not support SGL for all other algorithms. Signed-off-by: Ciara Power --- v2: - Chacha context was moved to qp_data rather than session. --- drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 14 +++++++++++--- drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 5 ++++- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c index bf434260c1..6d5d3ce8eb 100644 --- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c +++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c @@ -1200,10 +1200,12 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp, } if (op->sym->m_src->nb_segs > 1) { - if (session->cipher.mode != IMB_CIPHER_GCM) { + if (session->cipher.mode != IMB_CIPHER_GCM + && session->cipher.mode != + IMB_CIPHER_CHACHA20_POLY1305) { op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS; IPSEC_MB_LOG(ERR, "Device only supports SGL for AES-GCM" - " algorithm."); + " or CHACHA20_POLY1305 algorithms."); return -1; } sgl = 1; @@ -1296,6 +1298,11 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp, job->u.CHACHA20_POLY1305.aad = op->sym->aead.aad.data; job->u.CHACHA20_POLY1305.aad_len_in_bytes = session->aead.aad_len; + if (sgl) { + job->u.CHACHA20_POLY1305.ctx = &qp_data->chacha_sgl_ctx; + job->cipher_mode = IMB_CIPHER_CHACHA20_POLY1305_SGL; + job->hash_alg = IMB_AUTH_CHACHA20_POLY1305_SGL; + } job->enc_keys = session->cipher.expanded_aes_keys.encode; job->dec_keys = session->cipher.expanded_aes_keys.encode; break; @@ -1401,6 +1408,7 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp, break; case IMB_AUTH_GCM_SGL: + case IMB_AUTH_CHACHA20_POLY1305_SGL: job->hash_start_src_offset_in_bytes = 0; job->msg_len_to_hash_in_bytes = 0; job->iv = rte_crypto_op_ctod_offset(op, uint8_t *, @@ -1412,7 +1420,6 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp, op->sym->aead.data.offset; job->msg_len_to_hash_in_bytes = op->sym->aead.data.length; - job->iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); break; @@ -1498,6 +1505,7 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp, job->msg_len_to_cipher_in_bytes = op->sym->aead.data.length; break; case IMB_CIPHER_GCM_SGL: + case IMB_CIPHER_CHACHA20_POLY1305_SGL: job->msg_len_to_cipher_in_bytes = 0; job->cipher_start_src_offset_in_bytes = 0; break; diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h index 10e0b4c38e..9ef75aa51f 100644 --- a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h +++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h @@ -726,7 +726,10 @@ struct aesni_mb_qp_data { * by the driver when verifying a digest provided * by the user (using authentication verify operation) */ - struct gcm_context_data gcm_sgl_ctx; + union { + struct gcm_context_data gcm_sgl_ctx; + struct chacha20_poly1305_context_data chacha_sgl_ctx; + }; }; /* Maximum length for digest */