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Sun, 10 Apr 2022 02:25:35 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Subject: [PATCH 1/3] net/mlx5: fix setting flags to external RxQ Date: Sun, 10 Apr 2022 12:25:26 +0300 Message-ID: <20220410092528.1001685-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410092528.1001685-1-michaelba@nvidia.com> References: <20220410092528.1001685-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a8e8d04b-b1a3-4c19-213c-08da1ad41374 X-MS-TrafficTypeDiagnostic: MN2PR12MB4392:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: meXolAZmbiZwzNuwnt3mjBrcaTGColjYoFm34ehgKTSpW3LRHsMP6fdeuaPAYo5e6e9hYEfwwSFCcZvUz2qAJSWtwd5zm36s90YVptqTrjXqQQz6A2cAQzdXgTSiKiEAmve4OljxD3g7lng5UiwYqlgpjc4QVOVNkZL4mCUEcQt42/W17bJ0ijeCicrsF0Efxfva0awCyd6sdkcDpvtNKUkDZtWkKparoYS7Ziz1Ws6QQIh2CxnkFFa9bV8fg9kjo0esZNi8HLcnvBnKunQeExLc7T64hHrCTz3W3JoUgPZmZ6D0e3S2pe1aFv4Y7KOW4btk+vm8FU4DkwY28vwekiV0nBcGA+cZUvHZN6vCDLgJ8IUIOLUHQEpAbGsx/rOcITgC5nLYOjfhSPiH4+OW5b6HwIGzZSnIiiT+4NWElUDHLcTANJkMA6ZipX6hWFBAqppPAtBE0br8mx49R1uVQGmHtPxK3BaX4LKiwML/4eHDzW/eBTcwbL4Lprb+YXYiK1shT7A1ZFa9lfJ+5ddpTPAkJhz1+frUd+AvrgGhtZ0JwhOs0Hlfq4ELH0o0heFCfxC265iRHyqlkzpfvzEL2Q583162A3gLS7GUX4NVLmlsd86P0H0e9/wurjlimrBTOZe7GSCIl+68pnVVcewic875JzNBKmwcD//0NA53AGJeho+HqN3txVAGbt5XFIRlLddjmR93h6ACHqVPzNhWEw== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(2616005)(5660300002)(4326008)(8676002)(2906002)(86362001)(82310400005)(6666004)(7696005)(356005)(6286002)(8936002)(36756003)(508600001)(83380400001)(26005)(81166007)(316002)(55016003)(47076005)(186003)(6916009)(1076003)(40460700003)(336012)(426003)(54906003)(70586007)(450100002)(36860700001)(70206006)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2022 09:25:38.6394 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8e8d04b-b1a3-4c19-213c-08da1ad41374 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4392 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The flow_drv_rxq_flags_set sets the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device flow. It tries to get the RxQ control structure to update its ptype. however, external RxQs don't have control structure to update and it may cause a crash. This patch add check whether this Queue is external. Fixes: 311b17e669ab ("net/mlx5: support queue/RSS actions for external Rx queue") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 78cb38d42b..e7542afa80 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1379,8 +1379,11 @@ flow_drv_rxq_flags_set(struct rte_eth_dev *dev, return; for (i = 0; i != ind_tbl->queues_n; ++i) { int idx = ind_tbl->queues[i]; - struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); + struct mlx5_rxq_ctrl *rxq_ctrl; + if (mlx5_is_external_rxq(dev, idx)) + continue; + rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); MLX5_ASSERT(rxq_ctrl != NULL); if (rxq_ctrl == NULL) continue; @@ -1483,8 +1486,11 @@ flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, MLX5_ASSERT(dev->data->dev_started); for (i = 0; i != ind_tbl->queues_n; ++i) { int idx = ind_tbl->queues[i]; - struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); + struct mlx5_rxq_ctrl *rxq_ctrl; + if (mlx5_is_external_rxq(dev, idx)) + continue; + rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); MLX5_ASSERT(rxq_ctrl != NULL); if (rxq_ctrl == NULL) continue;