diff mbox series

[v1,2/4] common/mlx5: add modify ECN capability check

Message ID 20220402071150.9392-3-xiazhang@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers
Series Add support for modifying ECN in IPv4/IPv6 header |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Sean Zhang April 2, 2022, 7:11 a.m. UTC 
  Flag outer_ip_ecn in header modify capabilities properties layout is
added in order to check if the firmware supports modification of ecn
field.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c |  3 ++
 drivers/common/mlx5/mlx5_devx_cmds.h |  1 +
 drivers/common/mlx5/mlx5_prm.h       | 62 +++++++++++++++++++++++++++-
 3 files changed, 65 insertions(+), 1 deletion(-)

Comments

Slava Ovsiienko June 6, 2022, 8:05 a.m. UTC | #1 
> -----Original Message-----
> From: Sean Zhang (Networking SW) <xiazhang@nvidia.com>
> Sent: Saturday, April 2, 2022 10:12
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org
> Subject: [v1 2/4] common/mlx5: add modify ECN capability check
> 
> Flag outer_ip_ecn in header modify capabilities properties layout is added in
> order to check if the firmware supports modification of ecn field.
> 
> Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index d02ac2a678..72296c1ca3 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1047,6 +1047,9 @@  mlx5_devx_cmd_query_hca_attr(void *ctx,
 	attr->flow.tunnel_header_2_3 = MLX5_GET
 		(flow_table_nic_cap, hcattr,
 		 ft_field_support_2_nic_receive.tunnel_header_2_3);
+	attr->modify_outer_ip_ecn = MLX5_GET
+		(flow_table_nic_cap, hcattr,
+		 ft_header_modify_nic_receive.outer_ip_ecn);
 	attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 	attr->inner_ipv4_ihl = MLX5_GET
 		(flow_table_nic_cap, hcattr,
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 1bac18c59d..6e9e23f593 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -256,6 +256,7 @@  struct mlx5_hca_attr {
 	uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */
 	uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */
 	uint16_t max_wqe_sz_sq;
+	uint32_t modify_outer_ip_ecn:1;
 };
 
 /* LAG Context. */
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 44b18225f6..caaa4c7fb9 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -744,6 +744,7 @@  enum mlx5_modification_field {
 	MLX5_MODI_OUT_TCP_ACK_NUM,
 	MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 	MLX5_MODI_GTP_TEID = 0x6E,
+	MLX5_MODI_OUT_IP_ECN = 0x73,
 };
 
 /* Total number of metadata reg_c's. */
@@ -1884,6 +1885,62 @@  struct mlx5_ifc_roce_caps_bits {
 	u8 reserved_at_20[0x7e0];
 };
 
+struct mlx5_ifc_ft_fields_support_bits {
+	u8 outer_dmac[0x1];
+	u8 outer_smac[0x1];
+	u8 outer_ether_type[0x1];
+	u8 reserved_at_3[0x1];
+	u8 outer_first_prio[0x1];
+	u8 outer_first_cfi[0x1];
+	u8 outer_first_vid[0x1];
+	u8 reserved_at_7[0x1];
+	u8 outer_second_prio[0x1];
+	u8 outer_second_cfi[0x1];
+	u8 outer_second_vid[0x1];
+	u8 reserved_at_b[0x1];
+	u8 outer_sip[0x1];
+	u8 outer_dip[0x1];
+	u8 outer_frag[0x1];
+	u8 outer_ip_protocol[0x1];
+	u8 outer_ip_ecn[0x1];
+	u8 outer_ip_dscp[0x1];
+	u8 outer_udp_sport[0x1];
+	u8 outer_udp_dport[0x1];
+	u8 outer_tcp_sport[0x1];
+	u8 outer_tcp_dport[0x1];
+	u8 outer_tcp_flags[0x1];
+	u8 outer_gre_protocol[0x1];
+	u8 outer_gre_key[0x1];
+	u8 outer_vxlan_vni[0x1];
+	u8 reserved_at_1a[0x5];
+	u8 source_eswitch_port[0x1];
+	u8 inner_dmac[0x1];
+	u8 inner_smac[0x1];
+	u8 inner_ether_type[0x1];
+	u8 reserved_at_23[0x1];
+	u8 inner_first_prio[0x1];
+	u8 inner_first_cfi[0x1];
+	u8 inner_first_vid[0x1];
+	u8 reserved_at_27[0x1];
+	u8 inner_second_prio[0x1];
+	u8 inner_second_cfi[0x1];
+	u8 inner_second_vid[0x1];
+	u8 reserved_at_2b[0x1];
+	u8 inner_sip[0x1];
+	u8 inner_dip[0x1];
+	u8 inner_frag[0x1];
+	u8 inner_ip_protocol[0x1];
+	u8 inner_ip_ecn[0x1];
+	u8 inner_ip_dscp[0x1];
+	u8 inner_udp_sport[0x1];
+	u8 inner_udp_dport[0x1];
+	u8 inner_tcp_sport[0x1];
+	u8 inner_tcp_dport[0x1];
+	u8 inner_tcp_flags[0x1];
+	u8 reserved_at_37[0x9];
+	u8 reserved_at_40[0x40];
+};
+
 /*
  * Table 1872 - Flow Table Fields Supported 2 Format
  */
@@ -1923,7 +1980,10 @@  struct mlx5_ifc_flow_table_nic_cap_bits {
 		flow_table_properties_nic_transmit_rdma;
 	struct mlx5_ifc_flow_table_prop_layout_bits
 		flow_table_properties_nic_transmit_sniffer;
-	u8 reserved_at_e00[0x600];
+	u8 reserved_at_e00[0x200];
+	struct mlx5_ifc_ft_fields_support_bits
+		ft_header_modify_nic_receive;
+	u8 reserved_at_1080[0x380];
 	struct mlx5_ifc_ft_fields_support_2_bits
 		ft_field_support_2_nic_receive;
 };