From patchwork Thu Feb 24 13:40:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suanming Mou X-Patchwork-Id: 108281 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F802A034E; Thu, 24 Feb 2022 14:42:34 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F15AF4272B; Thu, 24 Feb 2022 14:41:49 +0100 (CET) Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam07on2085.outbound.protection.outlook.com [40.107.95.85]) by mails.dpdk.org (Postfix) with ESMTP id 74A6742709 for ; Thu, 24 Feb 2022 14:41:38 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=irQ/vsUzUxoImepoMpaSHUomT14zCo5Y0+NQ98GxSzOBwSP6ws3g59M7nbmhayGmbJPJQ4cC97BS94VTzMu9oLFO3aIAyhXTnA6Sj95iVmPzSLv8Vd7VwTgn6D0+439GvV1zAM8wu+OxNHS9viPO2R63pSLfgeYDNe2Qk7jSmrxgVHm5bBWsrv2si57pcgTqSrGx6laf5BgJH4Thi2otXFYi+V/hd6vXH7C9RY6QKw30mnB7/qJtDTDk8xDrEyBCKufo9mxMDP/K1Q7izcpVRTL9ASRh33tx3qbw6bL1RE7uFojO8HvWQjjHNwFcPtLzbiATl4KjvU9rS74l8AkwwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xbHEitJDrffkiGB2/UgQdwjD1Q84r1zBKm479RmVDpA=; b=Q+JLThHY3sPq/r1b0hHxJiLo2jK/5xEu5eFZqk2SY19EH6j4U1haVsZVOg8yU6xYUSsYkLKPUtprzj5AheWciqZpzL7Y6/svLxj+XRynjkdvYm4Rb9EHZPaMPvISr+THKBDzFa7GYo9EKBxnSYd17KIUOw45srAM3i/moBNo6WL6LTA/3+AHQey/T0XF89JEyCzUwmZWsRXR/mc6dgQ4FUb5P7qHtHcOr2cROM4iIJcTmArjBgW7XPg7SuU0kd1Aq0uMTgIVzmHoxM1kZGnbf8qrCVIv5cFrSyvAkMOMewN7xvSG0Iv3/yDKdD6e5cF9SqcZxNtgApHvVcjVqcWiDw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xbHEitJDrffkiGB2/UgQdwjD1Q84r1zBKm479RmVDpA=; b=iJZVDgTvyODZVP+KeBta+2lnD0C/C91CjzROgNR4TjQBcN2yNUwkML3eevH6tL1JEZCUG1PxIG8YcOhxruW4VUa0nFpNoDKOrC5wKNcxZv3D4EUxuhoNrs87iXFHYVZ2vtgrpmZXP3yAsJil6jExzJht4RsQ4bLnDpFNUUmgPkTqrz3kW0hAzA1xpMzFyqEfocN4WjcRdhBSbI/mnkP8Q+XuT/17m4C6/fpMrt9XbQrxoL2/uzfiSnNY7vcZDU1fZ1zan3DfAW1vKRDPDWGC+HY3jyBZd0Z4ymcGUTZr9XUDDasZ4oxtkweO2UrZdNjs+Sji7nErqDV8RVi2hw2uOw== Received: from DM3PR08CA0017.namprd08.prod.outlook.com (2603:10b6:0:52::27) by BYAPR12MB3416.namprd12.prod.outlook.com (2603:10b6:a03:ac::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4995.24; Thu, 24 Feb 2022 13:41:35 +0000 Received: from DM6NAM11FT034.eop-nam11.prod.protection.outlook.com (2603:10b6:0:52:cafe::f4) by DM3PR08CA0017.outlook.office365.com (2603:10b6:0:52::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5017.23 via Frontend Transport; Thu, 24 Feb 2022 13:41:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by DM6NAM11FT034.mail.protection.outlook.com (10.13.173.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5017.22 via Frontend Transport; Thu, 24 Feb 2022 13:41:35 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Feb 2022 13:41:29 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Thu, 24 Feb 2022 05:41:26 -0800 From: Suanming Mou To: , CC: , , Subject: [PATCH v4 09/14] net/mlx5: add flow flush function Date: Thu, 24 Feb 2022 15:40:46 +0200 Message-ID: <20220224134051.18167-10-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20220224134051.18167-1-suanmingm@nvidia.com> References: <20220210162926.20436-1-suanmingm@nvidia.com> <20220224134051.18167-1-suanmingm@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a8447296-4ab4-47ec-97e0-08d9f79b6056 X-MS-TrafficTypeDiagnostic: BYAPR12MB3416:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MHnhMbormOw4RN/wxnLD+K9lxe+NadAZZi9ZU1V0BTm53zMTRcD4LwQDep6g0JCjv+dIbyh7+q4ZfjyOSFAnEbh6DeOvIXdKnVys31x1ap5r8bERcP2iI0CNW6UX0tyvFjAFAc5o9sqbes9EOZc0xGsMCnTgytIPvJ6CSkVYZwqt4BlTxxUJG+0HhT7uDVDEXPzafgxfGLQqLw8XNHdoClNhVc/Qh3WxNj9E0gCcjS0Mt/SZeW1YMeNqKri4d/pLiM+NeMFkDYbxHWqUOdKmahN1chJLBzyhDKkkyACzPI0MKreZ+e45XBt/BlF0p7XIp31JwxS6zUNzDPh31NyFBCFmOoGDPcvzNwK1XUz9BQml5CMvlEsgIr3B5ritfmZ4gjK2K0tNXxAEFHE93Ofes10auZdP/VixiA+G1EEEu+vuzePLfNLPXA0opDUIy3ptFy55monvrPVc6gi4dvIMOsyDT3zMP+utigKaFRyuxatGwWJg0gP+/SJPNjkQpOENldB25NSwChTcm87IR0aNRxuUHKecsQEy3n+V8EgztX9BSCUu7pFtG5//f/f9tnJCBjl5D6i9RHHq091SrYRoyJcNXinDd9cT1WcYQjasBhu/IUNoktEw7sbztDVd9L2YprEWzKOseZX0PtWcHbQP9zM/mioZy2VzAG/Rm9InEXXKDUrFE7tZp9IGAGM25CEsPsQfFya5JZlGpT1z8eXpLQ== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(47076005)(54906003)(6636002)(36860700001)(83380400001)(110136005)(55016003)(316002)(40460700003)(70586007)(81166007)(1076003)(8676002)(6286002)(36756003)(16526019)(82310400004)(2906002)(508600001)(4326008)(86362001)(7696005)(2616005)(356005)(5660300002)(8936002)(70206006)(426003)(26005)(6666004)(186003)(336012)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2022 13:41:35.6352 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8447296-4ab4-47ec-97e0-08d9f79b6056 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3416 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In case port is being stopped, all created flows should be flushed. This commit adds the flow flush helper function. Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 8 ++ drivers/net/mlx5/mlx5_flow_hw.c | 129 ++++++++++++++++++++++++++++++++ 2 files changed, 137 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 1702d60fc0..5af71585fc 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -7024,6 +7024,14 @@ mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, uint32_t num_flushed = 0, fidx = 1; struct rte_flow *flow; +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + if (priv->sh->config.dv_flow_en == 2 && + type == MLX5_FLOW_TYPE_GEN) { + flow_hw_q_flow_flush(dev, NULL); + return; + } +#endif + MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { flow_list_destroy(dev, type, fidx); num_flushed++; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f0cb530524..74f8ee1d6a 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -13,6 +13,12 @@ /* The maximum actions support in the flow. */ #define MLX5_HW_MAX_ACTS 16 +/* Default push burst threshold. */ +#define BURST_THR 32u + +/* Default queue to flush the flows. */ +#define MLX5_DEFAULT_FLUSH_QUEUE 0 + const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops; /* DR action flags with different table. */ @@ -391,6 +397,129 @@ flow_hw_push(struct rte_eth_dev *dev, return 0; } +/** + * Drain the enqueued flows' completion. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] queue + * The queue to pull the flow. + * @param[in] pending_rules + * The pending flow number. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, negative value otherwise and rte_errno is set. + */ +static int +__flow_hw_pull_comp(struct rte_eth_dev *dev, + uint32_t queue, + uint32_t pending_rules, + struct rte_flow_error *error) +{ + struct rte_flow_op_result comp[BURST_THR]; + int ret, i, empty_loop = 0; + + flow_hw_push(dev, queue, error); + while (pending_rules) { + ret = flow_hw_pull(dev, queue, comp, BURST_THR, error); + if (ret < 0) + return -1; + if (!ret) { + rte_delay_us_sleep(20000); + if (++empty_loop > 5) { + DRV_LOG(WARNING, "No available dequeue, quit."); + break; + } + continue; + } + for (i = 0; i < ret; i++) { + if (comp[i].status == RTE_FLOW_OP_ERROR) + DRV_LOG(WARNING, "Flow flush get error CQE."); + } + if ((uint32_t)ret > pending_rules) { + DRV_LOG(WARNING, "Flow flush get extra CQE."); + return rte_flow_error_set(error, ERANGE, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "get extra CQE"); + } + pending_rules -= ret; + empty_loop = 0; + } + return 0; +} + +/** + * Flush created flows. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, negative value otherwise and rte_errno is set. + */ +int +flow_hw_q_flow_flush(struct rte_eth_dev *dev, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hw_q *hw_q; + struct rte_flow_template_table *tbl; + struct rte_flow_hw *flow; + struct rte_flow_op_attr attr = { + .postpone = 0, + }; + uint32_t pending_rules = 0; + uint32_t queue; + uint32_t fidx; + + /* + * Ensure to push and dequeue all the enqueued flow + * creation/destruction jobs in case user forgot to + * dequeue. Or the enqueued created flows will be + * leaked. The forgotten dequeues would also cause + * flow flush get extra CQEs as expected and pending_rules + * be minus value. + */ + for (queue = 0; queue < priv->nb_queue; queue++) { + hw_q = &priv->hw_q[queue]; + if (__flow_hw_pull_comp(dev, queue, hw_q->size - hw_q->job_idx, + error)) + return -1; + } + /* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */ + hw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE]; + LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) { + MLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) { + if (flow_hw_async_flow_destroy(dev, + MLX5_DEFAULT_FLUSH_QUEUE, + &attr, + (struct rte_flow *)flow, + NULL, + error)) + return -1; + pending_rules++; + /* Drain completion with queue size. */ + if (pending_rules >= hw_q->size) { + if (__flow_hw_pull_comp(dev, + MLX5_DEFAULT_FLUSH_QUEUE, + pending_rules, error)) + return -1; + pending_rules = 0; + } + } + } + /* Drain left completion. */ + if (pending_rules && + __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, pending_rules, + error)) + return -1; + return 0; +} + /** * Create flow table. *