common/cnxk: support B0 variant
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Commit Message
Add B0 variant to the list of supported models.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
drivers/common/cnxk/roc_model.c | 1 +
drivers/common/cnxk/roc_model.h | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
Comments
On Thu, Feb 24, 2022 at 4:13 PM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Add B0 variant to the list of supported models.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
Updated the git commit as follows and applied to
dpdk-next-net-mrvl/for-next-net. Thanks
common/cnxk: support CNF95xx B0 variant
Add CNF95xx B0 variant to the list of supported models.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> drivers/common/cnxk/roc_model.c | 1 +
> drivers/common/cnxk/roc_model.h | 6 ++++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
> index 49617c02b7..4120029541 100644
> --- a/drivers/common/cnxk/roc_model.c
> +++ b/drivers/common/cnxk/roc_model.c
> @@ -56,6 +56,7 @@ static const struct model_db {
> {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
> {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
> {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
> + {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
> {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
> {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
> "cnf95xxmm_a0"}};
> diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
> index cee06779bc..4567566169 100644
> --- a/drivers/common/cnxk/roc_model.h
> +++ b/drivers/common/cnxk/roc_model.h
> @@ -19,6 +19,7 @@ struct roc_model {
> #define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
> #define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
> #define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
> +#define ROC_MODEL_CNF95xxN_B0 BIT_ULL(15)
> #define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
> #define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
> #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
> @@ -39,11 +40,12 @@ struct roc_model {
> (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
> ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
> ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
> - ROC_MODEL_CNF95xxN_A1)
> + ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
> #define ROC_MODEL_CNF9K \
> (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 | \
> ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 | \
> - ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
> + ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 | \
> + ROC_MODEL_CNF95xxN_B0)
>
> #define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
> #define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
> --
> 2.25.1
>
On 2/24/2022 8:35 PM, Jerin Jacob wrote:
> On Thu, Feb 24, 2022 at 4:13 PM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>>
>> Add B0 variant to the list of supported models.
>>
>> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
>> Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>
> Updated the git commit as follows and applied to
> dpdk-next-net-mrvl/for-next-net. Thanks
>
> common/cnxk: support CNF95xx B0 variant
>
> Add CNF95xx B0 variant to the list of supported models.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
>
>
>> drivers/common/cnxk/roc_model.c | 1 +
>> drivers/common/cnxk/roc_model.h | 6 ++++--
>> 2 files changed, 5 insertions(+), 2 deletions(-)
Hi Jerin, Tomasz,
Can you please update release note to document this new
device support? (Although it is still B0, some users may be
interested in with the new device support.)
@@ -56,6 +56,7 @@ static const struct model_db {
{VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
{VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
{VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+ {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
{VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
{VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
"cnf95xxmm_a0"}};
@@ -19,6 +19,7 @@ struct roc_model {
#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
+#define ROC_MODEL_CNF95xxN_B0 BIT_ULL(15)
#define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
@@ -39,11 +40,12 @@ struct roc_model {
(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
- ROC_MODEL_CNF95xxN_A1)
+ ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
#define ROC_MODEL_CNF9K \
(ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 | \
ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 | \
- ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
+ ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 | \
+ ROC_MODEL_CNF95xxN_B0)
#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)