From patchwork Tue Feb 22 08:51:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suanming Mou X-Patchwork-Id: 107947 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCDF1A0350; Tue, 22 Feb 2022 09:53:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B4F70411DB; Tue, 22 Feb 2022 09:52:47 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2065.outbound.protection.outlook.com [40.107.220.65]) by mails.dpdk.org (Postfix) with ESMTP id E5FB4411A4 for ; Tue, 22 Feb 2022 09:52:44 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VdmwjtwbPAxU5eiRTvDU5As0shH3Q4GMVw7IWgKuuoI9QAu04cfr3zgG1+3myHxseyxNBfjtXgJ7+KP20zhQNwi3pX4rvfwpLqIBCWuYEtt9+4v1yuxZWrkO33YaCf+Pp08mOM4TYASigypJXCyMbb0rv9Bp/vNFl8b8nogO+U2jMSA1drJyDypwOOdg3RD/LMqDPJsjbvBozMyU8hVGzLfC8guGOahABpZ9yz9XIgu59g1v8tquBsPR74bnXh68/dHXFfqH2vHm4O28e57zbHcLhtVg16bZCgOYk6ybj/NWBqx7DIQMDNUPfIKyv9n2lknSj6CVenDABz7tw6YB0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=q3cC+vZaa7ITpMtrvifjNXrikIyHhtCcCwSgN1knl7Y=; b=Q+XVoC2STdb5wsF1xkMaqE7LtGOcg3IM2qDJUM8LLItGELlsl2IIJkDccWC5twdECbE/rV5v4pANCiGsIbDLQmVz9c73ca5xyIH95a3VDAnrVDoX/TfVKDLH+miQpwWWrFXsg0i1ZmKxJADFxrfcMh1GLZy2KFkaP62h56XPHgqNKh0BRBkd4t5VdkxDsQZAR9LD+EOK+I5Mi3ygzXD2mvNqUINEfTHSrZJnjmqQ1WfQUYcIMpdKEW98XiTsfxR97w7CMQ4MmejhczkMFFl4pnCY04eW26ZjhUmSRpV4btTXjS7l0/SB/UWfUfj7sSYpChIUz8TquIga2g1Z9x7Ryg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q3cC+vZaa7ITpMtrvifjNXrikIyHhtCcCwSgN1knl7Y=; b=oDrsomK666c1arx1/Az1aSpmO285I4hqeVmeq7iwO3KmMT56wtxdaWYB075IQhPJ7T6VS5ztkW5I2QJN7O+3kT/cKYa0ogPniUsMI0CJ41KHw7mRdCDslx4s66gaZzFPDq4XwK6pDXM6ybixzDsRZevfYv228V3u0dGZMvnPOMj5aplpcE6oh7BhLX7NGcCXoB78ye/QcpSsJqoTfw/jRia3UnQBh0bT+V2gnwIcDqdSd3D1DFaFVIeADBLZTGT5WLd9+On0JVb052Ji9CSw1A7yfNrTmG7iTWxNqKt0GFcpb0OM53oM+f3GgnAqHKWVqL3XQ3DePi7aVD0TnFXSPA== Received: from MWHPR19CA0023.namprd19.prod.outlook.com (2603:10b6:300:d4::33) by BN8PR12MB3010.namprd12.prod.outlook.com (2603:10b6:408:63::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4995.17; Tue, 22 Feb 2022 08:52:42 +0000 Received: from CO1NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:300:d4:cafe::bf) by MWHPR19CA0023.outlook.office365.com (2603:10b6:300:d4::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4995.27 via Frontend Transport; Tue, 22 Feb 2022 08:52:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT053.mail.protection.outlook.com (10.13.175.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4995.15 via Frontend Transport; Tue, 22 Feb 2022 08:52:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Feb 2022 08:52:40 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Tue, 22 Feb 2022 00:52:37 -0800 From: Suanming Mou To: , CC: , , Subject: [PATCH v2 12/14] net/mlx5: add mark action Date: Tue, 22 Feb 2022 10:51:54 +0200 Message-ID: <20220222085156.27137-13-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20220222085156.27137-1-suanmingm@nvidia.com> References: <20220210162926.20436-1-suanmingm@nvidia.com> <20220222085156.27137-1-suanmingm@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1e492b6e-8037-42ae-6c83-08d9f5e0afbf X-MS-TrafficTypeDiagnostic: BN8PR12MB3010:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fDj3Z4DdtkTfOitxNO47Ryb4rc58mnDHjubxhrjI+rLYOHAeyIkZsLuZSkqZXN0+CBkcMRsF1CXoqmhnxj2o+1Ri9JQVUJmq3xZAFbrhHwPc9O49JvT0MGYnVBwl21QqFHBKv4oeD1ruu8Axb141/9O8cxrs1TZi/JQ5MbMnXKRWDfY9a/Bxj/HRlf2WON+cq8MitkZG8QOUF06pogKeXVhh4GlAhBC8C37/5mX982lqNnsTx6DvsvQ3qr49sy7Mz2ds9Rp+N2BjmL0cLL0/EFr2UIFAupfHtrKUsAol2AhHNt7aQApWOOFywYQ1iDt8IhixvTLS5mjxa74twz6YrlkNcXkdoVdHpsMwBA8s270TyAdm3zMypav2rbFFWr0rg5KZIZbJIlUVd3fGQdWwlC0iy/BNxGw8cSZacIBec7SGkWFtj+jKP9yW4/EIiplU3zdxknqzeL2srMs38eSj1W24T+plovt65XtXBKY0Mdrk+ebZ8p1QTi3sevwAsWtraetLyhPeMMVmHz46A2HOaugTVhZlJisBpEemLabz/qB/pHz4Zyumhzdu8q4vKBkBEmLr7Ffigr5i8XoH2mw6TjLa906bsVW+19JieYVyXU4YPEdQqoTgPvfa0ZVjMMinncZcINvkN8/va/9gaGXPd5I77P1gX1i49zQsn1zIhvrVTsgvwlTrk3SnZD2SJi8EfuXMyt49XIhKbn1Zo6T+5A== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(356005)(110136005)(426003)(55016003)(54906003)(8676002)(4326008)(316002)(70586007)(86362001)(6636002)(26005)(336012)(186003)(1076003)(81166007)(70206006)(16526019)(6286002)(2616005)(83380400001)(47076005)(40460700003)(82310400004)(508600001)(5660300002)(36860700001)(7696005)(6666004)(36756003)(2906002)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2022 08:52:41.8579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e492b6e-8037-42ae-6c83-08d9f5e0afbf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3010 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mark action is covered by tag action internally. While it is added the HW will add a tag to the packet. The mark value can be set as fixed or dynamic as the action mask indicates. Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_flow.h | 1 + drivers/net/mlx5/mlx5_flow_hw.c | 66 ++++++++++++++++++++++++++++++--- 3 files changed, 63 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 43a913fcc5..e78eb5e380 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1528,6 +1528,8 @@ struct mlx5_priv { /* HW steering global drop action. */ struct mlx5dr_action *hw_drop[MLX5_HW_ACTION_FLAG_MAX] [MLX5DR_TABLE_TYPE_MAX]; + /* HW steering global drop action. */ + struct mlx5dr_action *hw_tag[MLX5_HW_ACTION_FLAG_MAX]; struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */ #endif }; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index aa1709e7cb..ec759c1aa4 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1077,6 +1077,7 @@ struct mlx5_hw_actions { struct mlx5_hw_jump_action *jump; /* Jump action. */ struct mlx5_hrxq *tir; /* TIR action. */ uint32_t acts_num:4; /* Total action number. */ + uint32_t mark:1; /* Indicate the mark action. */ /* Translated DR action array from action template. */ struct mlx5dr_rule_action rule_acts[MLX5_HW_MAX_ACTS]; }; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 0d49ab0bb2..a28e3c00b3 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -37,6 +37,31 @@ static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX] }, }; +/** + * Set rxq flag. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] enable + * Flag to enable or not. + */ +static void +flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable) +{ + struct mlx5_priv *priv = dev->data->dev_private; + unsigned int i; + + if ((!priv->mark_enabled && !enable) || + (priv->mark_enabled && enable)) + return; + for (i = 0; i < priv->rxqs_n; ++i) { + struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); + + rxq_ctrl->rxq.mark = enable; + } + priv->mark_enabled = enable; +} + /** * Register destination table DR jump action. * @@ -298,6 +323,20 @@ flow_hw_actions_translate(struct rte_eth_dev *dev, acts->rule_acts[i++].action = priv->hw_drop[!!attr->group][type]; break; + case RTE_FLOW_ACTION_TYPE_MARK: + acts->mark = true; + if (masks->conf) + acts->rule_acts[i].tag.value = + mlx5_flow_mark_set + (((const struct rte_flow_action_mark *) + (masks->conf))->id); + else if (__flow_hw_act_data_general_append(priv, acts, + actions->type, actions - action_start, i)) + goto err; + acts->rule_acts[i++].action = + priv->hw_tag[!!attr->group]; + flow_hw_rxq_flag_set(dev, true); + break; case RTE_FLOW_ACTION_TYPE_JUMP: if (masks->conf) { uint32_t jump_group = @@ -424,6 +463,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, } LIST_FOREACH(act_data, &hw_acts->act_list, next) { uint32_t jump_group; + uint32_t tag; struct mlx5_hw_jump_action *jump; struct mlx5_hrxq *hrxq; @@ -435,6 +475,12 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, break; case RTE_FLOW_ACTION_TYPE_VOID: break; + case RTE_FLOW_ACTION_TYPE_MARK: + tag = mlx5_flow_mark_set + (((const struct rte_flow_action_mark *) + (action->conf))->id); + rule_acts[act_data->action_dst].tag.value = tag; + break; case RTE_FLOW_ACTION_TYPE_JUMP: jump_group = ((const struct rte_flow_action_jump *) action->conf)->group; @@ -1027,6 +1073,8 @@ flow_hw_table_destroy(struct rte_eth_dev *dev, __atomic_sub_fetch(&table->its[i]->refcnt, 1, __ATOMIC_RELAXED); for (i = 0; i < table->nb_action_templates; i++) { + if (table->ats[i].acts.mark) + flow_hw_rxq_flag_set(dev, false); __flow_hw_action_template_destroy(dev, &table->ats[i].acts); __atomic_sub_fetch(&table->ats[i].action_template->refcnt, 1, __ATOMIC_RELAXED); @@ -1561,15 +1609,20 @@ flow_hw_configure(struct rte_eth_dev *dev, if (!priv->hw_drop[i][j]) goto err; } + priv->hw_tag[i] = mlx5dr_action_create_tag + (priv->dr_ctx, mlx5_hw_act_flag[i][0]); + if (!priv->hw_tag[i]) + goto err; } return 0; err: for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) { for (j = 0; j < MLX5DR_TABLE_TYPE_MAX; j++) { - if (!priv->hw_drop[i][j]) - continue; - mlx5dr_action_destroy(priv->hw_drop[i][j]); + if (priv->hw_drop[i][j]) + mlx5dr_action_destroy(priv->hw_drop[i][j]); } + if (priv->hw_tag[i]) + mlx5dr_action_destroy(priv->hw_tag[i]); } if (dr_ctx) claim_zero(mlx5dr_context_close(dr_ctx)); @@ -1615,10 +1668,11 @@ flow_hw_resource_release(struct rte_eth_dev *dev) } for (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) { for (j = 0; j < MLX5DR_TABLE_TYPE_MAX; j++) { - if (!priv->hw_drop[i][j]) - continue; - mlx5dr_action_destroy(priv->hw_drop[i][j]); + if (priv->hw_drop[i][j]) + mlx5dr_action_destroy(priv->hw_drop[i][j]); } + if (priv->hw_tag[i]) + mlx5dr_action_destroy(priv->hw_tag[i]); } if (priv->acts_ipool) { mlx5_ipool_destroy(priv->acts_ipool);