From patchwork Mon Jan 3 16:01:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 105585 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5E195A04A3; Mon, 3 Jan 2022 17:02:23 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A64E141148; Mon, 3 Jan 2022 17:02:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 132B040E0F for ; Mon, 3 Jan 2022 17:02:14 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 203CYs0R024887; Mon, 3 Jan 2022 08:02:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Zkq5S3lLnWq01ssAkq/zJmf8tJc5u1WV8PP9a4dBVHw=; b=YkTTzCHHhfpx3O+hxhLwSl0G/As/GT8pBV1imfNgflETLMILQm65WXjFigEYlzBTi2l2 X4PQTFTXWdKnJEon3kcxoWmZss28Ut0PvkMrv0phg0laHnkJy5GdyVHnni0uly8hVqkV fkyM6vSoXXJB3WXuI2YQ65+LCDdYSpfsEzyb16i4zVovk9iKGGqbiIQ9TLlaceikRD7l 6JF6HGPHAwh/XfA1Z/hpe5jOrDHngeG08HDd0Y23GO+jLgBIVqNNnHZRrDT6Fw4opaaR XGgQspuUhqzsNQeYWlc7AC+FLfQ+u61znxNV65eo//fWVQNWfhlxOlnDqmzyRqbvSuYF 0A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3dbmvswuva-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 03 Jan 2022 08:02:13 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Jan 2022 08:02:11 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 3 Jan 2022 08:02:11 -0800 Received: from localhost.localdomain (unknown [10.28.48.55]) by maili.marvell.com (Postfix) with ESMTP id C91653F706F; Mon, 3 Jan 2022 08:02:08 -0800 (PST) From: Akhil Goyal To: CC: , , , , , , , , Subject: [PATCH 1/5] common/cnxk: configure reassembly specific params Date: Mon, 3 Jan 2022 21:31:45 +0530 Message-ID: <20220103160149.1715058-2-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220103160149.1715058-1-gakhil@marvell.com> References: <20220103160149.1715058-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: J12sMGlgtjhwc0FmPUzijNGEM00U3qHx X-Proofpoint-GUID: J12sMGlgtjhwc0FmPUzijNGEM00U3qHx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-03_06,2022-01-01_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri When reassembly is enabled by application, set corresponding flags in SA during creation. Provide roc API to configure reassembly unit with active and zombie limits and step size Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/cnxk_security.c | 5 ++++- drivers/common/cnxk/roc_nix_inl.c | 23 +++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.h | 7 +++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c index 30562b46e3..9bd85fc4b4 100644 --- a/drivers/common/cnxk/cnxk_security.c +++ b/drivers/common/cnxk/cnxk_security.c @@ -295,9 +295,12 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa, * second pass meta and no defrag. */ sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META; - sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG; + sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG; sa->w0.s.pkind = ROC_OT_CPT_META_PKIND; + if (ipsec_xfrm->options.reass_en) + sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG; + /* ESN */ sa->w2.s.esn_en = !!ipsec_xfrm->options.esn; if (ipsec_xfrm->options.udp_encap) { diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index f0fc690417..6bfd10adde 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -200,6 +200,29 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi) return (sa_base + (spi * sz)); } +int +roc_nix_reass_configure(uint32_t max_wait_time, uint16_t max_frags) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct roc_cpt *roc_cpt; + struct roc_cpt_rxc_time_cfg *cfg; + + roc_cpt = idev->cpt; + if (!roc_cpt) { + plt_err("Cannot support inline inbound, cryptodev not probed"); + return -ENOTSUP; + } + + cfg->step = (max_wait_time / ROC_NIX_INL_REAS_ACTIVE_LIMIT) * 1000; + cfg->zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT; + cfg->zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD; + cfg->active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT; + cfg->active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD; + + roc_cpt_rxc_time_cfg(roc_cpt, cfg); + return 0; +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index abbeac684a..73a17276c4 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -43,6 +43,11 @@ /* Alignment of SA Base */ #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16) +#define ROC_NIX_INL_REAS_ACTIVE_LIMIT 0xFFF +#define ROC_NIX_INL_REAS_ACTIVE_THRESHOLD 10 +#define ROC_NIX_INL_REAS_ZOMBIE_LIMIT 0xFFF +#define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10 + static inline struct roc_onf_ipsec_inb_sa * roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx) { @@ -124,6 +129,8 @@ void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev); bool __roc_api roc_nix_inl_dev_is_probed(void); void __roc_api roc_nix_inl_dev_lock(void); void __roc_api roc_nix_inl_dev_unlock(void); +int __roc_api roc_nix_reass_configure(uint32_t max_wait_time, + uint16_t max_frags); /* NIX Inline Inbound API */ int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 07c6720f0c..9b04f3518a 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -203,6 +203,7 @@ INTERNAL { roc_nix_ptp_tx_ena_dis; roc_nix_queues_ctx_dump; roc_nix_ras_intr_ena_dis; + roc_nix_reass_configure; roc_nix_register_cq_irqs; roc_nix_register_queue_irqs; roc_nix_rq_dump;