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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT026.mail.protection.outlook.com (10.13.172.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4713.20 via Frontend Transport; Wed, 24 Nov 2021 09:36:15 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 24 Nov 2021 09:36:11 +0000 From: Dmitry Kozlyuk To: CC: Raslan Darawsheh , Matan Azrad , Viacheslav Ovsiienko Subject: [PATCH 1/2] net/mlx5: fix indirect RSS creation when port is stopped Date: Wed, 24 Nov 2021 11:35:52 +0200 Message-ID: <20211124093556.3358394-2-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211124093556.3358394-1-dkozlyuk@nvidia.com> References: <20211123223159.3324247-1-dkozlyuk@nvidia.com> <20211124093556.3358394-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5415f257-1588-4f40-9e80-08d9af2ddc64 X-MS-TrafficTypeDiagnostic: CY4PR12MB1798: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2000; 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Only increment reference counter when the port is started. Fixes: ec4e11d41d12 ("net/mlx5: preserve indirect actions on restart") Signed-off-by: Dmitry Kozlyuk --- drivers/net/mlx5/mlx5_rxq.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 47dc24793b..8f9a94572f 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2270,6 +2270,7 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, struct mlx5_ind_table_obj *ind_tbl) { struct mlx5_priv *priv = dev->data->dev_private; + bool dev_started = priv->dev_data->dev_started; uint32_t queues_n = ind_tbl->queues_n; uint16_t *queues = ind_tbl->queues; unsigned int i, j; @@ -2278,22 +2279,25 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, log2above(queues_n) : log2above(priv->config.ind_table_max_size); - for (i = 0; i != queues_n; ++i) { - if (mlx5_rxq_ref(dev, queues[i]) == NULL) { - ret = -rte_errno; - goto error; + if (dev_started) + for (i = 0; i != queues_n; ++i) { + if (mlx5_rxq_ref(dev, queues[i]) == NULL) { + ret = -rte_errno; + goto error; + } } - } ret = priv->obj_ops.ind_table_new(dev, n, ind_tbl); if (ret) goto error; __atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED); return 0; error: - err = rte_errno; - for (j = 0; j < i; j++) - mlx5_rxq_deref(dev, ind_tbl->queues[j]); - rte_errno = err; + if (dev_started) { + err = rte_errno; + for (j = 0; j < i; j++) + mlx5_rxq_deref(dev, queues[j]); + rte_errno = err; + } DRV_LOG(DEBUG, "Port %u cannot setup indirection table.", dev->data->port_id); return ret;