diff mbox series

net/mlx5: fix GRE item matching

Message ID 20211124043234.3287245-1-akozyrev@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: fix GRE item matching |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/github-robot: build success github build: passed

Commit Message

Alexander Kozyrev Nov. 24, 2021, 4:32 a.m. UTC 
  GRE protocol type is implicitly set in the matching translation in case
an application doesn't specify any type explicitly in a flow rule.
It is extracted from the inner header type, but this type may be absent.
In this case, GRE item matching is broken. Check if we have the inner
header type before setting it to allow matching on all GRE packets.

Fixes: be26e81bfc1c ("net/mlx5: fix GRE protocol type translation")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Slava Ovsiienko Nov. 24, 2021, 10:14 a.m. UTC | #1 
> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, November 24, 2021 6:33
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>;
> Gregory Etelson <getelson@nvidia.com>
> Subject: [PATCH] net/mlx5: fix GRE item matching
> 
> GRE protocol type is implicitly set in the matching translation in case an
> application doesn't specify any type explicitly in a flow rule.
> It is extracted from the inner header type, but this type may be absent.
> In this case, GRE item matching is broken. Check if we have the inner header
> type before setting it to allow matching on all GRE packets.
> 
> Fixes: be26e81bfc1c ("net/mlx5: fix GRE protocol type translation")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Raslan Darawsheh Nov. 24, 2021, 1:05 p.m. UTC | #2 
Hi,


> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, November 24, 2021 6:33 AM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>;
> Gregory Etelson <getelson@nvidia.com>
> Subject: [PATCH] net/mlx5: fix GRE item matching
> 
> GRE protocol type is implicitly set in the matching translation in case
> an application doesn't specify any type explicitly in a flow rule.
> It is extracted from the inner header type, but this type may be absent.
> In this case, GRE item matching is broken. Check if we have the inner
> header type before setting it to allow matching on all GRE packets.
> 
> Fixes: be26e81bfc1c ("net/mlx5: fix GRE protocol type translation")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
> ---

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 9d4bd0560c..7bb092ea9f 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -8823,8 +8823,9 @@  flow_dv_translate_item_gre(void *matcher, void *key,
 	protocol_v = rte_be_to_cpu_16(gre_v->protocol);
 	if (!protocol_m) {
 		/* Force next protocol to prevent matchers duplication */
-		protocol_m = 0xFFFF;
 		protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
+		if (protocol_v)
+			protocol_m = 0xFFFF;
 	}
 	MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,