@@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp,
}
rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX,
- tf_tbl_p4,
+ tf_tbl_p4[TF_DIR_RX],
(uint16_t *)resources->tbl_cnt);
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
- tbl_cfg.cfg = tf_tbl_p4;
+ tbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX];
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {
[CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope",
};
+struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
+ [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
+ 0, 0
+ },
+};
+
/**
* Device specific function that retrieves the MAX number of HCAPI
* types the device supports.
@@ -12,6 +12,8 @@
#include "tf_if_tbl.h"
#include "tf_global_cfg.h"
+extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX];
+
struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,
@@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
},
};
-struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
- [TF_TBL_TYPE_FULL_ACT_RECORD] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
- 0, 0
- },
- [TF_TBL_TYPE_MCAST_GROUPS] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_ENCAP_8B] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_ENCAP_16B] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_ENCAP_64B] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_SP_SMAC] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_STATS_64] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
- 0, 0
- },
- [TF_TBL_TYPE_METER_PROF] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
- 0, 0
- },
- [TF_TBL_TYPE_METER_INST] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
- 0, 0
- },
- [TF_TBL_TYPE_MIRROR_CONFIG] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
- 0, 0
- },
-
-};
-
struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_TBL_SCOPE] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,