@@ -1917,3 +1917,85 @@ int tf_query_sram_resources(struct tf *tfp,
return 0;
}
+
+int tf_set_sram_policy(struct tf *tfp,
+ struct tf_set_sram_policy_parms *parms)
+{
+ int rc = 0;
+ struct tf_dev_info dev;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* This function can be called before open session, filter
+ * out any non-supported device types on the Core side.
+ */
+ if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ TFP_DRV_LOG(ERR,
+ "Unsupported device type %d\n",
+ parms->device_type);
+ return -ENOTSUP;
+ }
+
+ tf_dev_bind_ops(parms->device_type, &dev);
+
+ if (dev.ops->tf_dev_set_sram_policy == NULL) {
+ rc = -EOPNOTSUPP;
+ TFP_DRV_LOG(ERR,
+ "%s: Operation not supported, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = dev.ops->tf_dev_set_sram_policy(parms->dir, parms->bank_id);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM policy set failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+
+ return rc;
+}
+
+int tf_get_sram_policy(struct tf *tfp,
+ struct tf_get_sram_policy_parms *parms)
+{
+ int rc = 0;
+ struct tf_dev_info dev;
+
+ TF_CHECK_PARMS2(tfp, parms);
+
+ /* This function can be called before open session, filter
+ * out any non-supported device types on the Core side.
+ */
+ if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ TFP_DRV_LOG(ERR,
+ "Unsupported device type %d\n",
+ parms->device_type);
+ return -ENOTSUP;
+ }
+
+ tf_dev_bind_ops(parms->device_type, &dev);
+
+ if (dev.ops->tf_dev_get_sram_policy == NULL) {
+ rc = -EOPNOTSUPP;
+ TFP_DRV_LOG(ERR,
+ "%s: Operation not supported, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = dev.ops->tf_dev_get_sram_policy(parms->dir, parms->bank_id);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "%s: SRAM policy get failed, rc:%s\n",
+ tf_dir_2_str(parms->dir),
+ strerror(-rc));
+ return rc;
+ }
+
+ return rc;
+}
@@ -2455,7 +2455,7 @@ int tf_get_version(struct tf *tfp,
*/
struct tf_query_sram_resources_parms {
/**
- * [in] device type
+ * [in] Device type
*
* Device type for the session.
*/
@@ -2501,4 +2501,68 @@ struct tf_query_sram_resources_parms {
int tf_query_sram_resources(struct tf *tfp,
struct tf_query_sram_resources_parms *parms);
+/**
+ * tf_set_sram_policy parameter definition
+ */
+struct tf_set_sram_policy_parms {
+ /**
+ * [in] Device type
+ *
+ * Device type for the session.
+ */
+ enum tf_device_type device_type;
+
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+
+ /**
+ * [in] Array of Bank id for each truflow tbl type
+ */
+ uint8_t *bank_id;
+};
+
+/**
+ * Set SRAM policy
+ *
+ * Used to assign SRAM bank index to all truflow table type.
+ *
+ * Returns success or failure code.
+ */
+int tf_set_sram_policy(struct tf *tfp,
+ struct tf_set_sram_policy_parms *parms);
+
+/**
+ * tf_get_sram_policy parameter definition
+ */
+struct tf_get_sram_policy_parms {
+ /**
+ * [in] Device type
+ *
+ * Device type for the session.
+ */
+ enum tf_device_type device_type;
+
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+
+ /**
+ * [out] Array of Bank id for each truflow tbl type
+ */
+ uint8_t bank_id[TF_TBL_TYPE_ACT_MODIFY_64B + 1];
+};
+
+/**
+ * Get SRAM policy
+ *
+ * Used to get the assigned bank of table types.
+ *
+ * Returns success or failure code.
+ */
+int tf_get_sram_policy(struct tf *tfp,
+ struct tf_get_sram_policy_parms *parms);
+
#endif /* _TF_CORE_H_ */
@@ -415,11 +415,14 @@ tf_dev_bind_p58(struct tf *tfp,
}
rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX,
- tf_tbl_p58,
+ tf_tbl_p58[TF_DIR_RX],
+ (uint16_t *)resources->tbl_cnt);
+ rsv_cnt += tf_dev_reservation_check(TF_TBL_TYPE_MAX,
+ tf_tbl_p58[TF_DIR_TX],
(uint16_t *)resources->tbl_cnt);
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
- tbl_cfg.cfg = tf_tbl_p58;
+ tbl_cfg.cfg = tf_tbl_p58[TF_DIR_RX];
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
@@ -1083,7 +1083,7 @@ struct tf_dev_ops {
uint32_t *em_caps);
/**
- * Device specific function that retrieve the sram resource
+ * Device specific function that retrieves the sram resource
*
* [in] query
* Point to resources query result
@@ -1101,6 +1101,38 @@ struct tf_dev_ops {
int (*tf_dev_get_sram_resources)(void *query,
uint32_t *sram_bank_caps,
bool *dynamic_sram_capable);
+
+ /**
+ * Device specific function that sets the sram policy
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [in] band_id
+ * SRAM bank id
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_set_sram_policy)(enum tf_dir dir,
+ uint8_t *bank_id);
+
+ /**
+ * Device specific function that gets the sram policy
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [in] band_id
+ * pointer to SRAM bank id
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+ int (*tf_dev_get_sram_policy)(enum tf_dir dir,
+ uint8_t *bank_id);
};
/**
@@ -383,7 +383,9 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
.tf_dev_get_mailbox = tf_dev_p4_get_mailbox,
.tf_dev_word_align = NULL,
.tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,
- .tf_dev_get_sram_resources = NULL
+ .tf_dev_get_sram_resources = NULL,
+ .tf_dev_set_sram_policy = NULL,
+ .tf_dev_get_sram_policy = NULL,
};
/**
@@ -447,5 +449,7 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_word_align = tf_dev_p4_word_align,
.tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash,
.tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps,
- .tf_dev_get_sram_resources = NULL
+ .tf_dev_get_sram_resources = NULL,
+ .tf_dev_set_sram_policy = NULL,
+ .tf_dev_get_sram_policy = NULL,
};
@@ -48,6 +48,235 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {
[CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc",
};
+struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
+ [TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METADATA] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
+ 0, 0
+ },
+ /* Policy - ARs in bank 1 */
+ [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
+ .slices = 4,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
+ .slices = 8,
+ },
+ /* Policy - Encaps in bank 2 */
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 8,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 4,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 1,
+ },
+ /* Policy - Modify in bank 2 with Encaps */
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 8,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 4,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 1,
+ },
+ /* Policy - SP in bank 0 */
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
+ .slices = 8,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
+ .slices = 4,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
+ .slices = 2,
+ },
+ /* Policy - Stats in bank 3 */
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
+ .slices = 8,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METADATA] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
+ 0, 0
+ },
+ /* Policy - ARs in bank 1 */
+ [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
+ .slices = 4,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
+ .slices = 8,
+ },
+ /* Policy - Encaps in bank 2 */
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 8,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 4,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 1,
+ },
+ /* Policy - Modify in bank 2 with Encaps */
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 8,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 4,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 1,
+ },
+ /* Policy - SP in bank 0 */
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
+ .slices = 8,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
+ .slices = 4,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
+ .slices = 2,
+ },
+ /* Policy - Stats in bank 3 */
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
+ .slices = 8,
+ },
+};
+
/**
* Device specific function that retrieves the MAX number of HCAPI
* types the device supports.
@@ -444,6 +673,80 @@ static int tf_dev_p58_get_sram_resources(void *q,
return 0;
}
+int sram_bank_hcapi_type[] = {
+ CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
+ CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
+ CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ CFA_RESOURCE_TYPE_P58_SRAM_BANK_3
+};
+
+/**
+ * Device specific function that set the sram policy
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [in] band_id
+ * SRAM bank id
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int tf_dev_p58_set_sram_policy(enum tf_dir dir,
+ uint8_t *bank_id)
+{
+ struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir];
+ uint8_t type;
+ uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF };
+
+ for (type = TF_TBL_TYPE_FULL_ACT_RECORD;
+ type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) {
+ if (bank_id[type] > 3)
+ return -EINVAL;
+
+ rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]];
+ if (parent[bank_id[type]] == 0xFF) {
+ parent[bank_id[type]] = type;
+ rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT;
+ rm_cfg[type].parent_subtype = 0;
+ if (rm_cfg[type].slices == 0)
+ rm_cfg[type].slices = 1;
+ } else {
+ rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD;
+ rm_cfg[type].parent_subtype = parent[bank_id[type]];
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * Device specific function that get the sram policy
+ *
+ * [in] dir
+ * Receive or transmit direction
+ *
+ * [out] band_id
+ * pointer to SRAM bank id
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+static int tf_dev_p58_get_sram_policy(enum tf_dir dir,
+ uint8_t *bank_id)
+{
+ struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir];
+ uint8_t type;
+
+ for (type = TF_TBL_TYPE_FULL_ACT_RECORD;
+ type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++)
+ bank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0;
+
+ return 0;
+}
+
/**
* Truflow P58 device specific functions
*/
@@ -495,7 +798,9 @@ const struct tf_dev_ops tf_dev_ops_p58_init = {
.tf_dev_get_mailbox = tf_dev_p58_get_mailbox,
.tf_dev_word_align = NULL,
.tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps,
- .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources
+ .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources,
+ .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy,
+ .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy,
};
/**
@@ -560,5 +865,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_word_align = tf_dev_p58_word_align,
.tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash,
.tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps,
- .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources
+ .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources,
+ .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy,
+ .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy,
};
@@ -12,6 +12,8 @@
#include "tf_if_tbl.h"
#include "tf_global_cfg.h"
+extern struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX];
+
struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH,
@@ -58,122 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
},
};
-struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
- [TF_TBL_TYPE_EM_FKB] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
- 0, 0
- },
- [TF_TBL_TYPE_WC_FKB] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
- 0, 0
- },
- [TF_TBL_TYPE_METER_PROF] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
- 0, 0
- },
- [TF_TBL_TYPE_METER_INST] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
- 0, 0
- },
- [TF_TBL_TYPE_METER_DROP_CNT] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
- 0, 0
- },
- [TF_TBL_TYPE_MIRROR_CONFIG] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
- 0, 0
- },
- [TF_TBL_TYPE_METADATA] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
- 0, 0
- },
- /* Policy - ARs in bank 1 */
- [TF_TBL_TYPE_FULL_ACT_RECORD] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 4,
- },
- [TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 8,
- },
- /* Policy - Encaps in bank 2 */
- [TF_TBL_TYPE_ACT_ENCAP_8B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
- },
- [TF_TBL_TYPE_ACT_ENCAP_16B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
- },
- [TF_TBL_TYPE_ACT_ENCAP_32B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
- },
- [TF_TBL_TYPE_ACT_ENCAP_64B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
- },
- /* Policy - Modify in bank 2 with Encaps */
- [TF_TBL_TYPE_ACT_MODIFY_8B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
- },
- [TF_TBL_TYPE_ACT_MODIFY_16B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
- },
- [TF_TBL_TYPE_ACT_MODIFY_32B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
- },
- [TF_TBL_TYPE_ACT_MODIFY_64B] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
- },
- /* Policy - SP in bank 0 */
- [TF_TBL_TYPE_ACT_SP_SMAC] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 8,
- },
- [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 4,
- },
- [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
- .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 2,
- },
- /* Policy - Stats in bank 3 */
- [TF_TBL_TYPE_ACT_STATS_64] = {
- .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
- .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 8,
- },
-};
-
struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_EM_RECORD] = {
TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC,
@@ -58,10 +58,10 @@ tf_tbl_bind(struct tf *tfp,
db_cfg.num_elements = parms->num_elements;
db_cfg.module = TF_MODULE_TYPE_TABLE;
db_cfg.num_elements = parms->num_elements;
- db_cfg.cfg = parms->cfg;
for (d = 0; d < TF_DIR_MAX; d++) {
db_cfg.dir = d;
+ db_cfg.cfg = &parms->cfg[d ? TF_TBL_TYPE_MAX : 0];
db_cfg.alloc_cnt = parms->resources->tbl_cnt[d].cnt;
db_cfg.rm_db = (void *)&tbl_db->tbl_db[d];
if (tf_session_is_shared_session(tfs) &&