From patchwork Fri Oct 22 17:03:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Zhang X-Patchwork-Id: 102686 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A88AA0C43; Fri, 22 Oct 2021 19:04:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9182B41109; Fri, 22 Oct 2021 19:04:11 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 60C2E410EA for ; Fri, 22 Oct 2021 19:04:02 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10145"; a="315546580" X-IronPort-AV: E=Sophos;i="5.87,173,1631602800"; d="scan'208";a="315546580" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2021 10:04:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,173,1631602800"; d="scan'208";a="569279767" Received: from silpixa00400885.ir.intel.com ([10.243.23.122]) by FMSMGA003.fm.intel.com with ESMTP; 22 Oct 2021 10:04:00 -0700 From: Fan Zhang To: dev@dpdk.org Cc: gakhil@marvell.com, Fan Zhang Date: Fri, 22 Oct 2021 18:03:48 +0100 Message-Id: <20211022170354.13503-4-roy.fan.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022170354.13503-1-roy.fan.zhang@intel.com> References: <20211014161137.1405168-1-roy.fan.zhang@intel.com> <20211022170354.13503-1-roy.fan.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [dpdk-dev v4 3/9] common/qat: add gen specific queue pair function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the queue pair data structure and function prototypes for different QAT generations. Signed-off-by: Fan Zhang Acked-by: Ciara Power --- drivers/common/qat/qat_qp.c | 3 ++ drivers/common/qat/qat_qp.h | 103 ++++++++++++++++++++++++------------ 2 files changed, 71 insertions(+), 35 deletions(-) diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c index b8c6000e86..27994036b8 100644 --- a/drivers/common/qat/qat_qp.c +++ b/drivers/common/qat/qat_qp.c @@ -34,6 +34,9 @@ ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \ (ADF_ARB_REG_SLOT * index), value) +struct qat_qp_hw_spec_funcs* + qat_qp_hw_spec[QAT_N_GENS]; + __extension__ const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES] [ADF_MAX_QPS_ON_ANY_SERVICE] = { diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h index e1627197fa..726cd2ef61 100644 --- a/drivers/common/qat/qat_qp.h +++ b/drivers/common/qat/qat_qp.h @@ -7,8 +7,6 @@ #include "qat_common.h" #include "adf_transport_access_macros.h" -struct qat_pci_device; - #define QAT_CSR_HEAD_WRITE_THRESH 32U /* number of requests to accumulate before writing head CSR */ @@ -24,37 +22,7 @@ struct qat_pci_device; #define QAT_GEN4_BUNDLE_NUM 4 #define QAT_GEN4_QPS_PER_BUNDLE_NUM 1 -/** - * Structure with data needed for creation of queue pair. - */ -struct qat_qp_hw_data { - enum qat_service_type service_type; - uint8_t hw_bundle_num; - uint8_t tx_ring_num; - uint8_t rx_ring_num; - uint16_t tx_msg_size; - uint16_t rx_msg_size; -}; - -/** - * Structure with data needed for creation of queue pair on gen4. - */ -struct qat_qp_gen4_data { - struct qat_qp_hw_data qat_qp_hw_data; - uint8_t reserved; - uint8_t valid; -}; - -/** - * Structure with data needed for creation of queue pair. - */ -struct qat_qp_config { - const struct qat_qp_hw_data *hw; - uint32_t nb_descriptors; - uint32_t cookie_size; - int socket_id; - const char *service_str; -}; +struct qat_pci_device; /** * Structure associated with each queue. @@ -96,8 +64,28 @@ struct qat_qp { uint16_t min_enq_burst_threshold; } __rte_cache_aligned; -extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE]; -extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE]; +/** + * Structure with data needed for creation of queue pair. + */ +struct qat_qp_hw_data { + enum qat_service_type service_type; + uint8_t hw_bundle_num; + uint8_t tx_ring_num; + uint8_t rx_ring_num; + uint16_t tx_msg_size; + uint16_t rx_msg_size; +}; + +/** + * Structure with data needed for creation of queue pair. + */ +struct qat_qp_config { + const struct qat_qp_hw_data *hw; + uint32_t nb_descriptors; + uint32_t cookie_size; + int socket_id; + const char *service_str; +}; uint16_t qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops); @@ -136,4 +124,49 @@ qat_select_valid_queue(struct qat_pci_device *qat_dev, int qp_id, int qat_read_qp_config(struct qat_pci_device *qat_dev); +/** + * Function prototypes for GENx specific queue pair operations. + **/ +typedef int (*qat_qp_rings_per_service_t) + (struct qat_pci_device *, enum qat_service_type); + +typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *); + +typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *, + rte_spinlock_t *); + +typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *, + rte_spinlock_t *); + +typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *); + +typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue *q); + +typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q, + uint32_t new_head); + +typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *, + struct qat_qp *); + +typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)( + struct qat_pci_device *dev, enum qat_service_type service_type, + uint16_t qp_id); + +struct qat_qp_hw_spec_funcs { + qat_qp_rings_per_service_t qat_qp_rings_per_service; + qat_qp_build_ring_base_t qat_qp_build_ring_base; + qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable; + qat_qp_adf_arb_disable_t qat_qp_adf_arb_disable; + qat_qp_adf_configure_queues_t qat_qp_adf_configure_queues; + qat_qp_csr_write_tail_t qat_qp_csr_write_tail; + qat_qp_csr_write_head_t qat_qp_csr_write_head; + qat_qp_csr_setup_t qat_qp_csr_setup; + qat_qp_get_hw_data_t qat_qp_get_hw_data; +}; + +extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[]; + +extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE]; +extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE]; + #endif /* _QAT_QP_H_ */