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gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT045.mail.protection.outlook.com (10.13.173.123) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Fri, 22 Oct 2021 15:46:26 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Oct 2021 15:46:23 +0000 From: Francis Kelly To: , Matan Azrad , "Viacheslav Ovsiienko" , Ori Kam CC: , , , Ady Agbarih Date: Fri, 22 Oct 2021 15:45:51 +0000 Message-ID: <20211022154600.2180938-1-fkelly@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c307478c-53bd-408d-c25c-08d995731b60 X-MS-TrafficTypeDiagnostic: DM6PR12MB3291: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2089; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(5660300002)(6636002)(36860700001)(1076003)(7636003)(36756003)(2906002)(86362001)(4326008)(6666004)(7696005)(6286002)(336012)(36906005)(54906003)(110136005)(15650500001)(16526019)(47076005)(83380400001)(316002)(186003)(26005)(55016002)(8676002)(82310400003)(508600001)(2616005)(356005)(426003)(70586007)(8936002)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2021 15:46:26.1550 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c307478c-53bd-408d-c25c-08d995731b60 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3291 Subject: [dpdk-dev] [PATCH 01/10] common/mlx5: update PRM definitions for regex availability X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ady Agbarih Update PRM hca capabilities definitions as follows: regexp_version field added - specifies whether BF2 or BF3 regexp field removed regexp_params field moved regexp_log_crspace_size field removed regexp_mmo added - specifies if using regex mmo wqe is supported Allow regex only if both regexp_params and regexp_mmo are set, instead of checking regexp_mmo only. Check version through the new capability field regexp_version instead of reading crspace register. Signed-off-by: Ady Agbarih Acked-by: Ori Kam --- drivers/common/mlx5/mlx5_devx_cmds.c | 3 ++- drivers/common/mlx5/mlx5_devx_cmds.h | 3 ++- drivers/common/mlx5/mlx5_prm.h | 12 +++++------- drivers/regex/mlx5/mlx5_regex.c | 11 ++--------- drivers/regex/mlx5/mlx5_rxp_csrs.h | 2 +- 5 files changed, 12 insertions(+), 19 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index fb7c8e986f..f0af94b31c 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -821,7 +821,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); attr->steering_format_version = MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); - attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); + attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); + attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, regexp_num_of_engines); /* Read the general_obj_types bitmap and extract the relevant bits. */ diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 5e4f3b749e..69b6bed2dd 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -151,7 +151,8 @@ struct mlx5_hca_attr { uint32_t sq_ts_format:2; uint32_t steering_format_version:4; uint32_t qp_ts_format:2; - uint32_t regex:1; + uint32_t regexp_params:1; + uint32_t regexp_version:3; uint32_t reg_c_preserve:1; uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ uint32_t crypto:1; /* Crypto engine is supported. */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index eab80eaead..8b0f2f1a89 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1341,16 +1341,13 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 wqe_index_ignore_cap[0x1]; u8 dynamic_qp_allocation[0x1]; u8 log_max_qp[0x5]; - u8 regexp[0x1]; - u8 reserved_at_a1[0x3]; + u8 reserved_at_a0[0x4]; u8 regexp_num_of_engines[0x4]; u8 reserved_at_a8[0x1]; u8 reg_c_preserve[0x1]; u8 reserved_at_aa[0x1]; u8 log_max_srq[0x5]; - u8 reserved_at_b0[0x3]; - u8 regexp_log_crspace_size[0x5]; - u8 reserved_at_b8[0x3]; + u8 reserved_at_b0[0xb]; u8 scatter_fcs_w_decap_disable[0x1]; u8 reserved_at_bc[0x4]; u8 reserved_at_c0[0x8]; @@ -1506,7 +1503,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 uc[0x1]; u8 rc[0x1]; u8 uar_4k[0x1]; - u8 reserved_at_241[0x9]; + u8 reserved_at_241[0x8]; + u8 regexp_params[0x1]; u8 uar_sz[0x6]; u8 port_selection_cap[0x1]; u8 reserved_at_251[0x7]; @@ -1523,7 +1521,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 max_wqe_sz_sq[0x10]; u8 reserved_at_2a0[0xc]; u8 regexp_mmo_sq[0x1]; - u8 reserved_at_2b0[0x3]; + u8 regexp_version[0x3]; u8 max_wqe_sz_rq[0x10]; u8 max_flow_counter_31_16[0x10]; u8 max_wqe_sz_sq_dc[0x10]; diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index 5aa988be6d..2124fd15f0 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -129,7 +129,6 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev) struct mlx5_hca_attr attr; char name[RTE_REGEXDEV_NAME_MAX_LEN]; int ret; - uint32_t val; ibv = mlx5_os_get_ibv_dev(rte_dev); if (ibv == NULL) @@ -146,7 +145,7 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev) DRV_LOG(ERR, "Unable to read HCA capabilities."); rte_errno = ENOTSUP; goto dev_error; - } else if (((!attr.regex) && (!attr.mmo_regex_sq_en) && + } else if (((!attr.regexp_params) && (!attr.mmo_regex_sq_en) && (!attr.mmo_regex_qp_en)) || attr.regexp_num_of_engines == 0) { DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe " "old FW/OFED version?"); @@ -170,13 +169,7 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev) priv->qp_ts_format = attr.qp_ts_format; priv->ctx = ctx; priv->nb_engines = 2; /* attr.regexp_num_of_engines */ - ret = mlx5_devx_regex_register_read(priv->ctx, 0, - MLX5_RXP_CSR_IDENTIFIER, &val); - if (ret) { - DRV_LOG(ERR, "CSR read failed!"); - goto dev_error; - } - if (val == MLX5_RXP_BF2_IDENTIFIER) + if (attr.regexp_version == MLX5_RXP_BF2_IDENTIFIER) priv->is_bf2 = 1; /* Default RXP programming mode to Shared. */ priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE; diff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h index f3ffdfdef2..08cb6f3261 100644 --- a/drivers/regex/mlx5/mlx5_rxp_csrs.h +++ b/drivers/regex/mlx5/mlx5_rxp_csrs.h @@ -6,7 +6,7 @@ #define _MLX5_RXP_CSRS_H_ /* BF types */ -#define MLX5_RXP_BF2_IDENTIFIER 0x07055254ul +#define MLX5_RXP_BF2_IDENTIFIER 0x0 /* * Common to all RXP implementations