From patchwork Thu Oct 14 16:11:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Zhang X-Patchwork-Id: 101648 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1A20A0C4B; Thu, 14 Oct 2021 18:18:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 75CF5411FE; Thu, 14 Oct 2021 18:17:58 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id C9FE141235 for ; Thu, 14 Oct 2021 18:17:55 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10137"; a="227998410" X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="227998410" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 09:11:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="527644548" Received: from silpixa00400885.ir.intel.com ([10.243.23.122]) by fmsmga008.fm.intel.com with ESMTP; 14 Oct 2021 09:11:40 -0700 From: Fan Zhang To: dev@dpdk.org Cc: gakhil@marvell.com, Fan Zhang , Arek Kusztal , Kai Ji Date: Thu, 14 Oct 2021 17:11:28 +0100 Message-Id: <20211014161137.1405168-2-roy.fan.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211014161137.1405168-1-roy.fan.zhang@intel.com> References: <20211001165954.717846-1-roy.fan.zhang@intel.com> <20211014161137.1405168-1-roy.fan.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [dpdk-dev v3 01/10] common/qat: add gen specific data and function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the data structure and function prototypes for different QAT generations. Signed-off-by: Arek Kusztal Signed-off-by: Fan Zhang Signed-off-by: Kai Ji --- drivers/common/qat/qat_common.h | 14 ++++++++------ drivers/common/qat/qat_device.c | 4 ++++ drivers/common/qat/qat_device.h | 23 +++++++++++++++++++++++ 3 files changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 23715085f4..1889ec4e88 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -15,20 +15,24 @@ /* Intel(R) QuickAssist Technology device generation is enumerated * from one according to the generation of the device */ + enum qat_device_gen { - QAT_GEN1 = 1, + QAT_GEN1, QAT_GEN2, QAT_GEN3, - QAT_GEN4 + QAT_GEN4, + QAT_N_GENS }; enum qat_service_type { - QAT_SERVICE_ASYMMETRIC = 0, + QAT_SERVICE_ASYMMETRIC, QAT_SERVICE_SYMMETRIC, QAT_SERVICE_COMPRESSION, - QAT_SERVICE_INVALID + QAT_MAX_SERVICES }; +#define QAT_SERVICE_INVALID (QAT_MAX_SERVICES) + enum qat_svc_list { QAT_SVC_UNUSED = 0, QAT_SVC_CRYPTO = 1, @@ -37,8 +41,6 @@ enum qat_svc_list { QAT_SVC_ASYM = 4, }; -#define QAT_MAX_SERVICES (QAT_SERVICE_INVALID) - /**< Common struct for scatter-gather list operations */ struct qat_flat_buf { uint32_t len; diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index 1b967cbcf7..e6b43c541f 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -13,6 +13,10 @@ #include "adf_pf2vf_msg.h" #include "qat_pf2vf.h" +/* Hardware device information per generation */ +struct qat_gen_hw_data qat_gen_config[QAT_N_GENS]; +struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[QAT_N_GENS]; + /* pv2vf data Gen 4*/ struct qat_pf2vf_dev qat_pf2vf_gen4 = { .pf2vf_offset = ADF_4XXXIOV_PF2VM_OFFSET, diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h index 228c057d1e..b8b5c387a3 100644 --- a/drivers/common/qat/qat_device.h +++ b/drivers/common/qat/qat_device.h @@ -21,6 +21,29 @@ #define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold" #define MAX_QP_THRESHOLD_SIZE 32 +/** + * Function prototypes for GENx specific device operations. + **/ +typedef int (*qat_dev_reset_ring_pairs_t) + (struct qat_pci_device *); +typedef const struct rte_mem_resource* (*qat_dev_get_transport_bar_t) + (struct rte_pci_device *); +typedef int (*qat_dev_get_misc_bar_t) + (struct rte_mem_resource **, struct rte_pci_device *); +typedef int (*qat_dev_read_config_t) + (struct qat_pci_device *); +typedef int (*qat_dev_get_extra_size_t)(void); + +struct qat_dev_hw_spec_funcs { + qat_dev_reset_ring_pairs_t qat_dev_reset_ring_pairs; + qat_dev_get_transport_bar_t qat_dev_get_transport_bar; + qat_dev_get_misc_bar_t qat_dev_get_misc_bar; + qat_dev_read_config_t qat_dev_read_config; + qat_dev_get_extra_size_t qat_dev_get_extra_size; +}; + +extern struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[]; + struct qat_dev_cmd_param { const char *name; uint16_t val;