From patchwork Sat Oct 9 01:39:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Zhang X-Patchwork-Id: 100881 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61FB6A034F; Sat, 9 Oct 2021 03:54:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5076241130; Sat, 9 Oct 2021 03:54:38 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id D8E6840E6E; Sat, 9 Oct 2021 03:54:35 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10131"; a="206739861" X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="206739861" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 18:54:35 -0700 X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="624917101" Received: from unknown (HELO intel-npg-odc-srv03.cd.intel.com) ([10.240.178.145]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 18:54:31 -0700 From: Robin Zhang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, helin.zhang@intel.com, jingjing.wu@intel.com, remy.horton@intel.com, jijiang.liu@intel.com, jing.d.chen@intel.com, cunming.liang@intel.com, wenzhuo.lu@intel.com, junfeng.guo@intel.com, stevex.yang@intel.com, Robin Zhang , stable@dpdk.org, Sylwester Dziedziuch Date: Sat, 9 Oct 2021 01:39:45 +0000 Message-Id: <20211009013956.70937-7-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211009013956.70937-1-robinx.zhang@intel.com> References: <20210618063851.3694702-1-robinx.zhang@intel.com> <20211009013956.70937-1-robinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 06/17] net/i40e/base: fix PF reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" PF has to delete all the filters during reset. If it is fully loaded with filters then it is possible that it will take more than 200 ms to finish the reset resulting in timeout during pf_reset and PF reset failed, -15 error indication. Increasing the timeout value for PF reset from 200 to 1000 to give PF more time to finish reset if it is loaded with filters. Fixes: 1e32378f0774 ("i40e/base: increase PF reset max loop limit") Cc: stable@dpdk.org Signed-off-by: Sylwester Dziedziuch Signed-off-by: Robin Zhang --- drivers/net/i40e/base/i40e_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index ceedec68bf..aa424e6010 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -1341,7 +1341,7 @@ STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw, return I40E_ERR_RESET_FAILED; } -#define I40E_PF_RESET_WAIT_COUNT 200 +#define I40E_PF_RESET_WAIT_COUNT 1000 /** * i40e_pf_reset - Reset the PF * @hw: pointer to the hardware structure