Add macros and structures for MAC frequency calculation in case the link
is not present.
Remove duplicate definition in i40e_ethdev.c
Signed-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>
Signed-off-by: Robin Zhang <robinx.zhang@intel.com>
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 9 +++++++++
drivers/net/i40e/base/i40e_register.h | 10 ++++++++++
drivers/net/i40e/base/i40e_type.h | 8 ++++++++
drivers/net/i40e/i40e_ethdev.c | 3 +--
4 files changed, 28 insertions(+), 2 deletions(-)
@@ -2035,6 +2035,15 @@ enum i40e_aq_link_speed {
I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
};
+enum i40e_prt_mac_pcs_link_speed {
+ I40E_PRT_MAC_PCS_LINK_SPEED_UNKNOWN = 0,
+ I40E_PRT_MAC_PCS_LINK_SPEED_100MB,
+ I40E_PRT_MAC_PCS_LINK_SPEED_1GB,
+ I40E_PRT_MAC_PCS_LINK_SPEED_10GB,
+ I40E_PRT_MAC_PCS_LINK_SPEED_40GB,
+ I40E_PRT_MAC_PCS_LINK_SPEED_20GB
+};
+
struct i40e_aqc_module_desc {
u8 oui[3];
u8 reserved1;
@@ -1411,6 +1411,11 @@
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
+/* _i=0...3 */ /* Reset: GLOBR */
+#define I40E_PRTMAC_PCS_LINK_STATUS1(_i) (0x0008C200 + ((_i) * 4))
+#define I40E_PRTMAC_PCS_LINK_STATUS1_LINK_SPEED_SHIFT 24
+#define I40E_PRTMAC_PCS_LINK_STATUS1_LINK_SPEED_MASK \
+ I40E_MASK(0x7, I40E_PRTMAC_PCS_LINK_STATUS1_LINK_SPEED_SHIFT)
#define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */
#define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0
#define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)
@@ -3873,6 +3878,11 @@
#define I40E_PRTMAC_LINK_DOWN_COUNTER 0x001E2440 /* Reset: GLOBR */
#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT 0
#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT)
+/* _i=0...3 */ /* Reset: GLOBR */
+#define I40E_PRTMAC_LINKSTA(_i) (0x001E2420 + ((_i) * 4))
+#define I40E_PRTMAC_LINKSTA_MAC_LINK_SPEED_SHIFT 27
+#define I40E_PRTMAC_LINKSTA_MAC_LINK_SPEED_MASK \
+ I40E_MASK(0x7, I40E_PRTMAC_LINKSTA_MAC_LINK_SPEED_SHIFT)
#define I40E_GLNVM_AL_REQ 0x000B6164 /* Reset: POR */
#define I40E_GLNVM_AL_REQ_POR_SHIFT 0
#define I40E_GLNVM_AL_REQ_POR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_POR_SHIFT)
@@ -236,6 +236,14 @@ enum i40e_queue_type {
I40E_QUEUE_TYPE_UNKNOWN
};
+enum i40e_prt_mac_link_speed {
+ I40E_PRT_MAC_LINK_SPEED_100MB = 0,
+ I40E_PRT_MAC_LINK_SPEED_1GB,
+ I40E_PRT_MAC_LINK_SPEED_10GB,
+ I40E_PRT_MAC_LINK_SPEED_40GB,
+ I40E_PRT_MAC_LINK_SPEED_20GB
+};
+
struct i40e_link_status {
enum i40e_aq_phy_type phy_type;
enum i40e_aq_link_speed link_speed;
@@ -2855,7 +2855,6 @@ static __rte_always_inline void
update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
{
/* Link status registers and values*/
-#define I40E_PRTMAC_LINKSTA 0x001E2420
#define I40E_REG_LINK_UP 0x40000080
#define I40E_PRTMAC_MACC 0x001E24E0
#define I40E_REG_MACC_25GB 0x00020000
@@ -2868,7 +2867,7 @@ update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
uint32_t link_speed;
uint32_t reg_val;
- reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
+ reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA(0));
link_speed = reg_val & I40E_REG_SPEED_MASK;
reg_val &= I40E_REG_LINK_UP;
link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;