From patchwork Fri Oct 8 10:41:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 100740 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BB7B9A0C43; Fri, 8 Oct 2021 04:56:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E3A3140696; Fri, 8 Oct 2021 04:56:07 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id CE6A94003C; Fri, 8 Oct 2021 04:56:05 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="207231558" X-IronPort-AV: E=Sophos;i="5.85,356,1624345200"; d="scan'208";a="207231558" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 19:56:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,356,1624345200"; d="scan'208";a="624559724" Received: from dpdk-junfengguo-v1.sh.intel.com ([10.67.119.231]) by fmsmga001.fm.intel.com with ESMTP; 07 Oct 2021 19:56:02 -0700 From: Junfeng Guo To: qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Cc: dev@dpdk.org, ferruh.yigit@intel.com, junfeng.guo@intel.com, stable@dpdk.org Date: Fri, 8 Oct 2021 10:41:43 +0000 Message-Id: <20211008104143.236289-1-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210929123134.1465507-1-junfeng.guo@intel.com> References: <20210929123134.1465507-1-junfeng.guo@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3] net/iavf: fix QFI field bit check for GTPU EH X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If GTPU Extionsion header has no pdu_type setting, the parsed value of gtp_psc_spec->hdr.type will be 0, which is same as IAVF_GTPU_EH_DWLINK. Thus, for this case, we should check gtp_psc_mask->hdr.type instead, to set QFI field bit of GTPU_EH first. Fixes: cd212c466992 ("net/iavf: fix QFI fields of GTPU UL/DL for flow director") Cc: stable@dpdk.org Signed-off-by: Junfeng Guo Acked-by: Qi Zhang --- drivers/net/iavf/iavf_fdir.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/iavf/iavf_fdir.c b/drivers/net/iavf/iavf_fdir.c index ea2b692712..ea99806330 100644 --- a/drivers/net/iavf/iavf_fdir.c +++ b/drivers/net/iavf/iavf_fdir.c @@ -1172,7 +1172,10 @@ iavf_fdir_parse_pattern(__rte_unused struct iavf_adapter *ad, if (gtp_psc_spec && gtp_psc_mask) { if (gtp_psc_mask->hdr.qfi == 0x3F) { input_set |= IAVF_INSET_GTPU_QFI; - if (gtp_psc_spec->hdr.type == + if (!gtp_psc_mask->hdr.type) + VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, + GTPU_EH, QFI); + else if (gtp_psc_spec->hdr.type == IAVF_GTPU_EH_UPLINK) VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_UP, QFI); @@ -1180,9 +1183,6 @@ iavf_fdir_parse_pattern(__rte_unused struct iavf_adapter *ad, IAVF_GTPU_EH_DWLINK) VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_DWN, QFI); - else - VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, - GTPU_EH, QFI); } rte_memcpy(hdr->buffer, gtp_psc_spec,