@@ -718,7 +718,7 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
fallback = true;
#else
fallback = false;
- if (!priv->config.devx || !priv->config.dv_flow_en ||
+ if (!sh->devx || !priv->config.dv_flow_en ||
!priv->config.hca_attr.flow_counters_dump ||
!(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
(mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
@@ -1025,7 +1025,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
sh = mlx5_alloc_shared_dev_ctx(spawn, config);
if (!sh)
return NULL;
- config->devx = sh->devx;
#ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
config->dest_tir = 1;
#endif
@@ -1325,7 +1324,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
config->mps == MLX5_MPW ? "legacy " : "",
config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
- if (config->devx) {
+ if (sh->devx) {
err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
if (err) {
err = -err;
@@ -1468,13 +1467,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->cqe_comp = 0;
}
if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&
- (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) {
+ (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) {
DRV_LOG(WARNING, "Flow Tag CQE compression"
" format isn't supported.");
config->cqe_comp = 0;
}
if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&
- (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) {
+ (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) {
DRV_LOG(WARNING, "L3/L4 Header CQE compression"
" format isn't supported.");
config->cqe_comp = 0;
@@ -1497,7 +1496,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->hca_attr.log_max_static_sq_wq);
DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported",
config->hca_attr.qos.wqe_rate_pp ? "" : "not ");
- if (!config->devx) {
+ if (!sh->devx) {
DRV_LOG(ERR, "DevX is required for packet pacing");
err = ENODEV;
goto error;
@@ -1544,7 +1543,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
goto error;
#endif
}
- if (config->devx) {
+ if (sh->devx) {
uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
err = config->hca_attr.access_register_user ?
@@ -1722,7 +1721,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
if (err)
goto error;
}
- if (config->devx && config->dv_flow_en && config->dest_tir) {
+ if (sh->devx && config->dv_flow_en && config->dest_tir) {
priv->obj_ops = devx_obj_ops;
priv->obj_ops.drop_action_create =
ibv_obj_ops.drop_action_create;
@@ -265,7 +265,6 @@ struct mlx5_dev_config {
unsigned int lacp_by_user:1;
/* Enable user to manage LACP traffic. */
unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
- unsigned int devx:1; /* Whether devx interface is available or not. */
unsigned int dest_tir:1; /* Whether advanced DR API is available. */
unsigned int reclaim_mode:2; /* Memory reclaim mode. */
unsigned int rt_timestamp:1; /* realtime timestamp format. */
@@ -3350,7 +3350,7 @@ flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
{
struct mlx5_priv *priv = dev->data->dev_private;
- if (!priv->config.devx)
+ if (!priv->sh->devx)
goto notsup_err;
if (action_flags & MLX5_FLOW_ACTION_COUNT)
return rte_flow_error_set(error, EINVAL,
@@ -5297,7 +5297,7 @@ flow_dv_validate_action_age(uint64_t action_flags,
struct mlx5_priv *priv = dev->data->dev_private;
const struct rte_flow_action_age *age = action->conf;
- if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
+ if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
!priv->sh->aso_age_mng))
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
@@ -5582,7 +5582,7 @@ flow_dv_validate_action_sample(uint64_t *action_flags,
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ACTION, action,
"ratio value starts from 1");
- if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
+ if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
NULL,
@@ -6166,7 +6166,7 @@ flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
uint32_t cnt_idx;
- if (!priv->config.devx) {
+ if (!priv->sh->devx) {
rte_errno = ENOTSUP;
return 0;
}
@@ -6553,7 +6553,7 @@ flow_dv_mtr_alloc(struct rte_eth_dev *dev)
struct mlx5_aso_mtr_pool *pool;
uint32_t mtr_idx = 0;
- if (!priv->config.devx) {
+ if (!priv->sh->devx) {
rte_errno = ENOTSUP;
return 0;
}
@@ -12438,7 +12438,7 @@ flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
uint32_t ct_idx;
MLX5_ASSERT(mng);
- if (!priv->config.devx) {
+ if (!priv->sh->devx) {
rte_errno = ENOTSUP;
return 0;
}
@@ -12874,7 +12874,7 @@ flow_dv_translate(struct rte_eth_dev *dev,
}
break;
case RTE_FLOW_ACTION_TYPE_COUNT:
- if (!dev_conf->devx) {
+ if (!priv->sh->devx) {
return rte_flow_error_set
(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
@@ -15718,7 +15718,7 @@ flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
struct mlx5_priv *priv = dev->data->dev_private;
struct rte_flow_query_count *qc = data;
- if (!priv->config.devx)
+ if (!priv->sh->devx)
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
NULL,
@@ -17331,7 +17331,7 @@ flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
uint64_t inn_pkts, inn_bytes;
int ret;
- if (!priv->config.devx)
+ if (!priv->sh->devx)
return -1;
ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
@@ -1112,7 +1112,7 @@ mlx5_dev_start(struct rte_eth_dev *dev)
dev->data->port_id, strerror(rte_errno));
goto error;
}
- if ((priv->config.devx && priv->config.dv_flow_en &&
+ if ((priv->sh->devx && priv->config.dv_flow_en &&
priv->config.dest_tir) && priv->obj_ops.lb_dummy_queue_create) {
ret = priv->obj_ops.lb_dummy_queue_create(dev);
if (ret)
@@ -272,7 +272,7 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
fallback = true;
#else
fallback = false;
- if (!priv->config.devx || !priv->config.dv_flow_en ||
+ if (!sh->devx || !priv->config.dv_flow_en ||
!priv->config.hca_attr.flow_counters_dump ||
!(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
(mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
@@ -349,7 +349,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
sh = mlx5_alloc_shared_dev_ctx(spawn, config);
if (!sh)
return NULL;
- config->devx = sh->devx;
/* Initialize the shutdown event in mlx5_dev_spawn to
* support mlx5_is_removed for Windows.
*/
@@ -452,7 +451,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
config->cqe_comp = 0;
}
- if (config->devx) {
+ if (sh->devx) {
err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
if (err) {
err = -err;
@@ -471,7 +470,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
DRV_LOG(DEBUG, "checksum offloading is %ssupported",
(config->hw_csum ? "" : "not "));
}
- if (config->devx) {
+ if (sh->devx) {
uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
err = config->hca_attr.access_register_user ?
@@ -642,7 +641,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
goto error;
}
}
- if (config->devx && config->dv_flow_en) {
+ if (sh->devx && config->dv_flow_en) {
priv->obj_ops = devx_obj_ops;
} else {
DRV_LOG(ERR, "Flow mode %u is not supported "