From patchwork Mon Oct 4 10:03:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 100421 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 642B3A0C4C; Mon, 4 Oct 2021 12:03:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51FDE4130D; Mon, 4 Oct 2021 12:03:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E7D7B41307 for ; Mon, 4 Oct 2021 12:03:21 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1948CIkY013065; Mon, 4 Oct 2021 03:03:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=I5JCtCi9+oWE/UPnG6J2tdqs2KtG1xVuHfFzeS2GzU8=; b=CGfkxHUU0ESSEPY0Sq8lNSC3OHYDm9/BkjrAbB7nhYSinH2NPcpkpyFOouyNRX9aygog gmWtTCytpH1FOdlHX0slg0wuAyD27SUX7TH9KOle0Gu5ZQ6fVnSDPFvV5B1rhrfvgdSU s/1/tK2R2GvZtRNlOdTMjgr27xTbNs97hcZ9vllKMLWeQ+vQ6V45G/rIkEq9GjTy3XeM 6eTfgfAGGTmCpK0mBkn69DN37ndDQU8PTdTs5OHfxncPQBBkboSn+Z4KhbxtuOwXjf+E FtOp1ek/jypS/jm0e4igYLRWeEgOjQal4KgzVHSWqYTm6sXgWK6xUxMT2u+OVzYeSN8q Jg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bfc9yaa2f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 04 Oct 2021 03:03:18 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 4 Oct 2021 03:03:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 4 Oct 2021 03:03:17 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 440E55B6950; Mon, 4 Oct 2021 03:03:15 -0700 (PDT) From: To: , Ruifeng Wang CC: , Pavan Nikhilesh Date: Mon, 4 Oct 2021 15:33:03 +0530 Message-ID: <20211004100304.13602-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-GUID: I8ksJeN9-xaFJj4ViogWffeuSXhUJq4Z X-Proofpoint-ORIG-GUID: I8ksJeN9-xaFJj4ViogWffeuSXhUJq4Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-04_02,2021-10-01_02,2020-04-07_01 Subject: [dpdk-dev] [RFC] eal/arm: remove CASP constraints for GCC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh GCC now assigns even register pairs for CASP, the fix has also been backported to all stable releases of older GCC versions. Removing the manual register allocation allows GCC to inline the functions and pick optimal registers for performing CASP. Signed-off-by: Pavan Nikhilesh --- lib/eal/arm/include/rte_atomic_64.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/lib/eal/arm/include/rte_atomic_64.h b/lib/eal/arm/include/rte_atomic_64.h index fa6f334c0d..f6f31ae777 100644 --- a/lib/eal/arm/include/rte_atomic_64.h +++ b/lib/eal/arm/include/rte_atomic_64.h @@ -52,6 +52,7 @@ rte_atomic_thread_fence(int memorder) #define __LSE_PREAMBLE "" #endif +#if defined(__clang__) #define __ATOMIC128_CAS_OP(cas_op_name, op_string) \ static __rte_noinline void \ cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \ @@ -76,6 +77,19 @@ cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \ old->val[0] = x0; \ old->val[1] = x1; \ } +#else +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) \ +static __rte_always_inline void \ +cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \ +{ \ + asm volatile( \ + __LSE_PREAMBLE \ + op_string " %[old], %H[old], %[upd], %H[upd], [%[dst]]" \ + : [old] "+r"(old->int128) \ + : [upd] "r"(updated.int128), [dst] "r"(dst) \ + : "memory"); \ +} +#endif __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp") __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")