[v4,2/2] hash: unify crc32 selection for x86 and Arm
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Commit Message
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
Merge crc32 hash calculation public API implementation for x86 and Arm.
Select the best available CRC32 algorithm when unsupported algorithm
on a given CPU architecture is requested by an application.
Previously, if an application directly includes `rte_crc_arm64.h`
without including `rte_hash_crc.h` it will fail to compile.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
lib/hash/hash_crc_arm64.h | 48 ++++++++++
lib/hash/meson.build | 1 -
lib/hash/rte_crc_arm64.h | 183 --------------------------------------
lib/hash/rte_hash_crc.h | 81 +++++++++++++----
4 files changed, 112 insertions(+), 201 deletions(-)
create mode 100644 lib/hash/hash_crc_arm64.h
delete mode 100644 lib/hash/rte_crc_arm64.h
Comments
> -----Original Message-----
> From: pbhagavatula@marvell.com <pbhagavatula@marvell.com>
> Sent: Monday, October 4, 2021 1:53 PM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>;
> konstantin.ananyev@intel.com; jerinj@marvell.com; Yipeng Wang
> <yipeng1.wang@intel.com>; Sameh Gobriel <sameh.gobriel@intel.com>;
> Bruce Richardson <bruce.richardson@intel.com>; Vladimir Medvedkin
> <vladimir.medvedkin@intel.com>
> Cc: dev@dpdk.org; Pavan Nikhilesh <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v4 2/2] hash: unify crc32 selection for x86 and
> Arm
>
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>
> Merge crc32 hash calculation public API implementation for x86 and Arm.
> Select the best available CRC32 algorithm when unsupported algorithm on a
> given CPU architecture is requested by an application.
>
> Previously, if an application directly includes `rte_crc_arm64.h` without
> including `rte_hash_crc.h` it will fail to compile.
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
> lib/hash/hash_crc_arm64.h | 48 ++++++++++
> lib/hash/meson.build | 1 -
> lib/hash/rte_crc_arm64.h | 183 --------------------------------------
> lib/hash/rte_hash_crc.h | 81 +++++++++++++----
> 4 files changed, 112 insertions(+), 201 deletions(-) create mode 100644
> lib/hash/hash_crc_arm64.h delete mode 100644 lib/hash/rte_crc_arm64.h
>
<snip>
> diff --git a/lib/hash/rte_hash_crc.h b/lib/hash/rte_hash_crc.h index
> 1cc8f84fe2..a51f6d3cc4 100644
> --- a/lib/hash/rte_hash_crc.h
> +++ b/lib/hash/rte_hash_crc.h
> @@ -16,10 +16,18 @@ extern "C" {
> #endif
>
> #include <stdint.h>
> -#include <rte_config.h>
> -#include <rte_cpuflags.h>
> +
> #include <rte_branch_prediction.h>
> #include <rte_common.h>
> +#include <rte_config.h>
> +#include <rte_cpuflags.h>
> +#include <rte_log.h>
> +
> +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
> #include
> +"hash_crc_arm64.h"
> +#elif defined(RTE_ARCH_X86)
> +#include "hash_crc_x86.h"
> +#endif
>
> #include <hash_crc_sw.h>
>
> @@ -31,37 +39,64 @@ extern "C" {
>
> static uint8_t crc32_alg = CRC32_SW;
>
> -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32) -
> #include "rte_crc_arm64.h"
> -#else
> -#include "hash_crc_x86.h"
> -
> /**
> - * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash
> + * Allow or disallow use of SSE4.2/ARMv8 intrinsics for CRC32 hash
> * calculation.
> *
> * @param alg
> * An OR of following flags:
> - * - (CRC32_SW) Don't use SSE4.2 intrinsics
> + * - (CRC32_SW) Don't use SSE4.2/ARMv8 intrinsics (default non-
> [x86/ARMv8])
> * - (CRC32_SSE42) Use SSE4.2 intrinsics if available
> - * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default)
> + * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default x86)
> + * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available (default ARMv8)
> *
> */
> static inline void
> rte_hash_crc_set_alg(uint8_t alg)
hash_crc_arm64.h and hash_crc_x86.h are there. How about leaving only function declaration in rte_hash_crc.h, and
have implementations in arch specific files?
By this way, ifdefs in the implementation can be dropped.
> {
> -#if defined(RTE_ARCH_X86)
> - if (alg == CRC32_SSE42_x64 &&
> - !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
> - alg = CRC32_SSE42;
> + switch (alg) {
> + case CRC32_SSE42_x64:
> + case CRC32_SSE42:
> +#if defined RTE_ARCH_X86
> + if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
> + crc32_alg = CRC32_SSE42;
> + else
> + crc32_alg = alg;
> +#endif
> +#if defined RTE_ARCH_ARM64
> + RTE_LOG(WARNING, HASH,
> + "Incorrect CRC32 algorithm requested setting best
> available algorithm on the architecture\n");
> + rte_hash_crc_set_alg(CRC32_ARM64);
> #endif
> - crc32_alg = alg;
> + break;
> + case CRC32_ARM64:
> +#if defined RTE_ARCH_ARM64
> + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32))
> + crc32_alg = CRC32_ARM64;
> +#endif
> +#if defined RTE_ARCH_X86
> + RTE_LOG(WARNING, HASH,
> + "Incorrect CRC32 algorithm requested setting best
> available algorithm on the architecture\n");
> + rte_hash_crc_set_alg(CRC32_SSE42_x64);
> +#endif
> + break;
> + case CRC32_SW:
> + default:
> + crc32_alg = CRC32_SW;
> + break;
> + }
> }
>
> /* Setting the best available algorithm */
> RTE_INIT(rte_hash_crc_init_alg)
> {
> +#if defined(RTE_ARCH_X86)
> rte_hash_crc_set_alg(CRC32_SSE42_x64);
> +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
> + rte_hash_crc_set_alg(CRC32_ARM64);
> +#else
> + rte_hash_crc_set_alg(CRC32_SW);
> +#endif
> }
>
> /**
> @@ -82,6 +117,9 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val) #if
Same for these APIs.
> defined RTE_ARCH_X86
> if (likely(crc32_alg & CRC32_SSE42))
> return crc32c_sse42_u8(data, init_val);
> +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
> + if (likely(crc32_alg & CRC32_ARM64))
> + return crc32c_arm64_u8(data, init_val);
> #endif
>
> return crc32c_1byte(data, init_val);
> @@ -105,6 +143,9 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
> #if defined RTE_ARCH_X86
> if (likely(crc32_alg & CRC32_SSE42))
> return crc32c_sse42_u16(data, init_val);
> +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
> + if (likely(crc32_alg & CRC32_ARM64))
> + return crc32c_arm64_u16(data, init_val);
> #endif
>
> return crc32c_2bytes(data, init_val);
> @@ -128,6 +169,9 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
> #if defined RTE_ARCH_X86
> if (likely(crc32_alg & CRC32_SSE42))
> return crc32c_sse42_u32(data, init_val);
> +#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
> + if (likely(crc32_alg & CRC32_ARM64))
> + return crc32c_arm64_u32(data, init_val);
> #endif
>
> return crc32c_1word(data, init_val);
> @@ -158,11 +202,14 @@ rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
> return crc32c_sse42_u64_mimic(data, init_val); #endif
>
> +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
> + if (likely(crc32_alg & CRC32_ARM64))
> + return crc32c_arm64_u64(data, init_val); #endif
> +
> return crc32c_2words(data, init_val);
> }
>
> -#endif
> -
> /**
> * Calculate CRC32 hash on user-supplied byte array.
> *
> --
> 2.17.1
new file mode 100644
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ */
+
+#ifndef _HASH_CRC_ARM64_H_
+#define _HASH_CRC_ARM64_H_
+
+static inline uint32_t
+crc32c_arm64_u8(uint8_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32cb %w[crc], %w[crc], %w[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+static inline uint32_t
+crc32c_arm64_u16(uint16_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32ch %w[crc], %w[crc], %w[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+static inline uint32_t
+crc32c_arm64_u32(uint32_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32cw %w[crc], %w[crc], %w[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+static inline uint32_t
+crc32c_arm64_u64(uint64_t data, uint32_t init_val)
+{
+ __asm__ volatile(
+ "crc32cx %w[crc], %w[crc], %x[value]"
+ : [crc] "+r" (init_val)
+ : [value] "r" (data));
+ return init_val;
+}
+
+#endif /* _HASH_CRC_ARM64_H_ */
@@ -8,7 +8,6 @@ headers = files(
'rte_jhash.h',
'rte_thash.h',
)
-indirect_headers += files('rte_crc_arm64.h')
sources = files('rte_cuckoo_hash.c', 'rte_fbk_hash.c', 'rte_thash.c')
deps += ['net']
deleted file mode 100644
@@ -1,183 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015 Cavium, Inc
- */
-
-#ifndef _RTE_CRC_ARM64_H_
-#define _RTE_CRC_ARM64_H_
-
-/**
- * @file
- *
- * RTE CRC arm64 Hash
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <rte_cpuflags.h>
-#include <rte_branch_prediction.h>
-#include <rte_common.h>
-
-static inline uint32_t
-crc32c_arm64_u8(uint8_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32cb %w[crc], %w[crc], %w[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-static inline uint32_t
-crc32c_arm64_u16(uint16_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32ch %w[crc], %w[crc], %w[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-static inline uint32_t
-crc32c_arm64_u32(uint32_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32cw %w[crc], %w[crc], %w[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-static inline uint32_t
-crc32c_arm64_u64(uint64_t data, uint32_t init_val)
-{
- __asm__ volatile(
- "crc32cx %w[crc], %w[crc], %x[value]"
- : [crc] "+r" (init_val)
- : [value] "r" (data));
- return init_val;
-}
-
-/**
- * Allow or disallow use of arm64 SIMD instrinsics for CRC32 hash
- * calculation.
- *
- * @param alg
- * An OR of following flags:
- * - (CRC32_SW) Don't use arm64 crc intrinsics
- * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available
- *
- */
-static inline void
-rte_hash_crc_set_alg(uint8_t alg)
-{
- switch (alg) {
- case CRC32_ARM64:
- if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32))
- alg = CRC32_SW;
- /* fall-through */
- case CRC32_SW:
- crc32_alg = alg;
- /* fall-through */
- default:
- break;
- }
-}
-
-/* Setting the best available algorithm */
-RTE_INIT(rte_hash_crc_init_alg)
-{
- rte_hash_crc_set_alg(CRC32_ARM64);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 1 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
-{
- if (likely(crc32_alg & CRC32_ARM64))
- return crc32c_arm64_u8(data, init_val);
-
- return crc32c_1byte(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 2 bytes value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
-{
- if (likely(crc32_alg & CRC32_ARM64))
- return crc32c_arm64_u16(data, init_val);
-
- return crc32c_2bytes(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 4 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
-{
- if (likely(crc32_alg & CRC32_ARM64))
- return crc32c_arm64_u32(data, init_val);
-
- return crc32c_1word(data, init_val);
-}
-
-/**
- * Use single crc32 instruction to perform a hash on a 8 byte value.
- * Fall back to software crc32 implementation in case arm64 crc intrinsics is
- * not supported
- *
- * @param data
- * Data to perform hash on.
- * @param init_val
- * Value to initialise hash generator.
- * @return
- * 32bit calculated hash value.
- */
-static inline uint32_t
-rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
-{
- if (likely(crc32_alg == CRC32_ARM64))
- return crc32c_arm64_u64(data, init_val);
-
- return crc32c_2words(data, init_val);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _RTE_CRC_ARM64_H_ */
@@ -16,10 +16,18 @@ extern "C" {
#endif
#include <stdint.h>
-#include <rte_config.h>
-#include <rte_cpuflags.h>
+
#include <rte_branch_prediction.h>
#include <rte_common.h>
+#include <rte_config.h>
+#include <rte_cpuflags.h>
+#include <rte_log.h>
+
+#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+#include "hash_crc_arm64.h"
+#elif defined(RTE_ARCH_X86)
+#include "hash_crc_x86.h"
+#endif
#include <hash_crc_sw.h>
@@ -31,37 +39,64 @@ extern "C" {
static uint8_t crc32_alg = CRC32_SW;
-#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
-#include "rte_crc_arm64.h"
-#else
-#include "hash_crc_x86.h"
-
/**
- * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash
+ * Allow or disallow use of SSE4.2/ARMv8 intrinsics for CRC32 hash
* calculation.
*
* @param alg
* An OR of following flags:
- * - (CRC32_SW) Don't use SSE4.2 intrinsics
+ * - (CRC32_SW) Don't use SSE4.2/ARMv8 intrinsics (default non-[x86/ARMv8])
* - (CRC32_SSE42) Use SSE4.2 intrinsics if available
- * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default)
+ * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default x86)
+ * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available (default ARMv8)
*
*/
static inline void
rte_hash_crc_set_alg(uint8_t alg)
{
-#if defined(RTE_ARCH_X86)
- if (alg == CRC32_SSE42_x64 &&
- !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
- alg = CRC32_SSE42;
+ switch (alg) {
+ case CRC32_SSE42_x64:
+ case CRC32_SSE42:
+#if defined RTE_ARCH_X86
+ if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))
+ crc32_alg = CRC32_SSE42;
+ else
+ crc32_alg = alg;
+#endif
+#if defined RTE_ARCH_ARM64
+ RTE_LOG(WARNING, HASH,
+ "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n");
+ rte_hash_crc_set_alg(CRC32_ARM64);
#endif
- crc32_alg = alg;
+ break;
+ case CRC32_ARM64:
+#if defined RTE_ARCH_ARM64
+ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32))
+ crc32_alg = CRC32_ARM64;
+#endif
+#if defined RTE_ARCH_X86
+ RTE_LOG(WARNING, HASH,
+ "Incorrect CRC32 algorithm requested setting best available algorithm on the architecture\n");
+ rte_hash_crc_set_alg(CRC32_SSE42_x64);
+#endif
+ break;
+ case CRC32_SW:
+ default:
+ crc32_alg = CRC32_SW;
+ break;
+ }
}
/* Setting the best available algorithm */
RTE_INIT(rte_hash_crc_init_alg)
{
+#if defined(RTE_ARCH_X86)
rte_hash_crc_set_alg(CRC32_SSE42_x64);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ rte_hash_crc_set_alg(CRC32_ARM64);
+#else
+ rte_hash_crc_set_alg(CRC32_SW);
+#endif
}
/**
@@ -82,6 +117,9 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val)
#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u8(data, init_val);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u8(data, init_val);
#endif
return crc32c_1byte(data, init_val);
@@ -105,6 +143,9 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val)
#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u16(data, init_val);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u16(data, init_val);
#endif
return crc32c_2bytes(data, init_val);
@@ -128,6 +169,9 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
#if defined RTE_ARCH_X86
if (likely(crc32_alg & CRC32_SSE42))
return crc32c_sse42_u32(data, init_val);
+#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u32(data, init_val);
#endif
return crc32c_1word(data, init_val);
@@ -158,11 +202,14 @@ rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
return crc32c_sse42_u64_mimic(data, init_val);
#endif
+#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRC32)
+ if (likely(crc32_alg & CRC32_ARM64))
+ return crc32c_arm64_u64(data, init_val);
+#endif
+
return crc32c_2words(data, init_val);
}
-#endif
-
/**
* Calculate CRC32 hash on user-supplied byte array.
*