diff mbox series

[v2,03/10] common/qat: add gen specific queue pair function

Message ID 20211001165954.717846-4-roy.fan.zhang@intel.com (mailing list archive)
State Changes Requested, archived
Delegated to: akhil goyal
Headers
Series drivers/qat: isolate implementations of qat generations |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Fan Zhang Oct. 1, 2021, 4:59 p.m. UTC 
  This patch adds the queue pair data structure and function
prototypes for different QAT generations.

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
---
 drivers/common/qat/qat_qp.c |  3 +++
 drivers/common/qat/qat_qp.h | 45 +++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)
diff mbox series

Patch

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index b8c6000e86..27994036b8 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -34,6 +34,9 @@ 
 	ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
 	(ADF_ARB_REG_SLOT * index), value)
 
+struct qat_qp_hw_spec_funcs*
+	qat_qp_hw_spec[QAT_N_GENS];
+
 __extension__
 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
 					 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index e1627197fa..2de66b888b 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -8,6 +8,51 @@ 
 #include "adf_transport_access_macros.h"
 
 struct qat_pci_device;
+struct qat_qp_hw_data;
+struct qat_queue;
+struct qat_qp;
+
+/**
+ * Function prototypes for GENx specific queue pair operations.
+ **/
+typedef int (*qat_qp_rings_per_service_t)
+		(struct qat_pci_device *, enum qat_service_type);
+
+typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
+
+typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
+		rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
+		rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
+
+typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue *q);
+
+typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
+		uint32_t new_head);
+
+typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
+		struct qat_qp *);
+
+typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
+		struct qat_pci_device *dev, enum qat_service_type service_type,
+		uint16_t qp_id);
+
+struct qat_qp_hw_spec_funcs {
+	qat_qp_rings_per_service_t	qat_qp_rings_per_service;
+	qat_qp_build_ring_base_t	qat_qp_build_ring_base;
+	qat_qp_adf_arb_enable_t		qat_qp_adf_arb_enable;
+	qat_qp_adf_arb_disable_t	qat_qp_adf_arb_disable;
+	qat_qp_adf_configure_queues_t	qat_qp_adf_configure_queues;
+	qat_qp_csr_write_tail_t		qat_qp_csr_write_tail;
+	qat_qp_csr_write_head_t		qat_qp_csr_write_head;
+	qat_qp_csr_setup_t		qat_qp_csr_setup;
+	qat_qp_get_hw_data_t		qat_qp_get_hw_data;
+};
+
+extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
 
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */