From patchwork Mon Sep 27 08:22:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 99724 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BB992A0547; Mon, 27 Sep 2021 10:23:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C00E4111F; Mon, 27 Sep 2021 10:22:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 90C4F41104 for ; Mon, 27 Sep 2021 10:22:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18QNq9wA030898; Mon, 27 Sep 2021 01:22:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=+5b/9kJ3dTi36Z+xWTpG6X9x7aBgPAImLsvlgV8Bv9k=; b=W+ipOIuNIvqP3+bmAfVdAFNkVn2wNCeWCrf0iMvsLybNgAK0aHC+Ae+BzFLIArM0EpJa irOmoH5D76oziEMvQkD3kfR3Cm2bP8DLCjLDrnXrNUiWez4iqgCNj7TR5yU54n4QtxXt fgWFzb5z34Alz/4mR4I6ON9x7CV50ROyZKYqcA86TLaeTcqw04je1vAHrRbIwnzEsuNM VR8BVbk34kVubaKUNLd5gBWaP7jCqcemSE8GDHpVBQp1Pf0dC2iUsTMvC3NNb3aPUXdK 17yQYz0h6eEozcfnZqjN9tNx9y6At1Q5ZSkYvyCy8EhRqqLIn7yTJOlrE15UR/xQ7PE0 Aw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bavvuhts6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 27 Sep 2021 01:22:46 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 27 Sep 2021 01:22:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 27 Sep 2021 01:22:44 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id A24343F70A0; Mon, 27 Sep 2021 01:22:42 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Mon, 27 Sep 2021 13:52:03 +0530 Message-ID: <20210927082223.757436-7-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210927082223.757436-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: hAiCyEketYHsL5KuYCUYsezvA6Catnox X-Proofpoint-GUID: hAiCyEketYHsL5KuYCUYsezvA6Catnox X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-27_02,2021-09-24_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 07/27] common/cnxk: support RoC API to toggle profile state X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC API to enable or disable HW bandwidth profiles on CN10K platform. Signed-off-by: Sunil Kumar Kori --- v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 4 ++++ drivers/common/cnxk/roc_nix_bpf.c | 39 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 44 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index af9bbb659c..b4995cd014 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -262,6 +262,7 @@ struct roc_nix_stats_queue { struct roc_nix_rq { /* Input parameters */ uint16_t qid; + uint16_t bpf_id; uint64_t aura_handle; bool ipsech_ena; uint16_t first_skip; @@ -607,6 +608,9 @@ int __roc_api roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, enum roc_nix_bpf_level_flag lvl_flag, struct roc_nix_bpf_cfg *cfg); +int __roc_api roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, + struct roc_nix_rq *rq, bool enable); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index b1a427caaf..4dcf4cd5b9 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -441,3 +441,42 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, return mbox_process(mbox); } + +int +roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, struct roc_nix_rq *rq, + bool enable) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_req *aq; + int rc; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + if (rq->qid >= nix->nb_rx_queues) + return NIX_ERR_QUEUE_INVALID_RANGE; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = rq->qid; + aq->ctype = NIX_AQ_CTYPE_RQ; + aq->op = NIX_AQ_INSTOP_WRITE; + + aq->rq.policer_ena = enable; + aq->rq_mask.policer_ena = ~(aq->rq_mask.policer_ena); + if (enable) { + aq->rq.band_prof_id = id; + aq->rq_mask.band_prof_id = ~(aq->rq_mask.band_prof_id); + } + + rc = mbox_process(mbox); + if (rc) + goto exit; + + rq->bpf_id = id; + +exit: + return rc; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 6a009eaf35..4c5adb8212 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -80,6 +80,7 @@ INTERNAL { roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_count_get; + roc_nix_bpf_ena_dis; roc_nix_bpf_free; roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx;