From patchwork Fri Sep 24 08:56:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 99549 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 33382A0548; Fri, 24 Sep 2021 10:57:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A41434122D; Fri, 24 Sep 2021 10:57:04 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 53E9740142 for ; Fri, 24 Sep 2021 10:57:03 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10116"; a="222145294" X-IronPort-AV: E=Sophos;i="5.85,319,1624345200"; d="scan'208";a="222145294" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2021 01:57:00 -0700 X-IronPort-AV: E=Sophos;i="5.85,319,1624345200"; d="scan'208";a="534947681" Received: from shwdenpg235.ccr.corp.intel.com ([10.253.106.22]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2021 01:56:59 -0700 From: Alvin Zhang To: qi.z.zhang@intel.com Cc: dev@dpdk.org, Alvin Zhang Date: Fri, 24 Sep 2021 16:56:53 +0800 Message-Id: <20210924085653.17080-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20210918025923.5112-1-alvinx.zhang@intel.com> References: <20210918025923.5112-1-alvinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3] net/ice: add support for low Rx latency X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds a devarg parameter to enable/disable low Rx latency. Signed-off-by: Alvin Zhang --- v3: rebase to dpdk-next-net-intel --- doc/guides/nics/ice.rst | 12 ++++++++++++ drivers/net/ice/ice_ethdev.c | 26 +++++++++++++++++++++++--- drivers/net/ice/ice_ethdev.h | 1 + 3 files changed, 36 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst index ebe2cbc..355f192 100644 --- a/doc/guides/nics/ice.rst +++ b/doc/guides/nics/ice.rst @@ -227,6 +227,18 @@ Runtime Config Options -a af:00.0,pps_out='[pin:0]' +- ``Low Rx latency`` (default ``0``) + + vRAN workloads require low latency DPDK interface for the front haul + interface connection to Radio. By specifying ``1`` for parameter + ``rx-low-latency``, each completed Rx descriptor can be written immediately + to host memory and the Rx interrupt latency can be reduced to 2us:: + + -a 0000:88:00.0,rx-low-latency=1 + + As a trade-off, this configuration may cause the packet processing performance + degradation due to the PCI bandwidth limitation. + Driver compilation and testing ------------------------------ diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index e24a3b6..9edf811 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -30,6 +30,7 @@ #define ICE_PROTO_XTR_ARG "proto_xtr" #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" #define ICE_ONE_PPS_OUT_ARG "pps_out" +#define ICE_RX_LOW_LATENCY "rx-low-latency" static const char * const ice_valid_args[] = { ICE_SAFE_MODE_SUPPORT_ARG, @@ -37,6 +38,7 @@ ICE_PROTO_XTR_ARG, ICE_HW_DEBUG_MASK_ARG, ICE_ONE_PPS_OUT_ARG, + ICE_RX_LOW_LATENCY, NULL }; @@ -1956,6 +1958,9 @@ static int ice_parse_devargs(struct rte_eth_dev *dev) if (ret) goto bail; + ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY, + &parse_bool, &ad->devargs.rx_low_latency); + bail: rte_kvargs_free(kvlist); return ret; @@ -3272,8 +3277,9 @@ static int ice_init_rss(struct ice_pf *pf) { struct ice_hw *hw = ICE_VSI_TO_HW(vsi); uint32_t val, val_tx; - int i; + int rx_low_latency, i; + rx_low_latency = vsi->adapter->devargs.rx_low_latency; for (i = 0; i < nb_queue; i++) { /*do actual bind*/ val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | @@ -3283,8 +3289,21 @@ static int ice_init_rss(struct ice_pf *pf) PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", base_queue + i, msix_vect); + /* set ITR0 value */ - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); + if (rx_low_latency) { + /** + * Empirical configuration for optimal real time + * latency reduced interrupt throttling to 2us + */ + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1); + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), + QRX_ITR_NO_EXPR_M); + } else { + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0); + } + ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); } @@ -5497,7 +5516,8 @@ static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, ICE_HW_DEBUG_MASK_ARG "=0xXXX" ICE_PROTO_XTR_ARG "=[queue:]" ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" - ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); + ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>" + ICE_RX_LOW_LATENCY "=<0|1>"); RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE); RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE); diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index ea9d892..26f5c56 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -476,6 +476,7 @@ struct ice_pf { * Cache devargs parse result. */ struct ice_devargs { + int rx_low_latency; int safe_mode_support; uint8_t proto_xtr_dflt; int pipe_mode_support;