diff mbox series

[V5,4/4] examples/pipeline: add learner table example

Message ID 20210920150133.84928-4-cristian.dumitrescu@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers show
Series [V5,1/4] table: add support learner tables | expand

Checks

Context Check Description
ci/Intel-compilation fail Compilation issues
ci/checkpatch success coding style OK

Commit Message

Cristian Dumitrescu Sept. 20, 2021, 3:01 p.m. UTC
Added the files to illustrate the learner table usage.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---

V2: Added description to the .spec file.

 examples/pipeline/examples/learner.cli  |  37 +++++++
 examples/pipeline/examples/learner.spec | 127 ++++++++++++++++++++++++
 2 files changed, 164 insertions(+)
 create mode 100644 examples/pipeline/examples/learner.cli
 create mode 100644 examples/pipeline/examples/learner.spec
diff mbox series

Patch

diff --git a/examples/pipeline/examples/learner.cli b/examples/pipeline/examples/learner.cli
new file mode 100644
index 0000000000..af7792624f
--- /dev/null
+++ b/examples/pipeline/examples/learner.cli
@@ -0,0 +1,37 @@ 
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2020 Intel Corporation
+
+;
+; Customize the LINK parameters to match your setup.
+;
+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
+
+link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+
+;
+; PIPELINE0 setup.
+;
+pipeline PIPELINE0 create 0
+
+pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32
+pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32
+pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32
+pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32
+
+pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
+pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
+pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
+pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
+pipeline PIPELINE0 port out 4 sink none
+
+pipeline PIPELINE0 build ./examples/pipeline/examples/learner.spec
+
+;
+; Pipelines-to-threads mapping.
+;
+thread 1 pipeline PIPELINE0 enable
+
+; Once the application has started, the command to get the CLI prompt is: telnet 0.0.0.0 8086
diff --git a/examples/pipeline/examples/learner.spec b/examples/pipeline/examples/learner.spec
new file mode 100644
index 0000000000..d635422282
--- /dev/null
+++ b/examples/pipeline/examples/learner.spec
@@ -0,0 +1,127 @@ 
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2020 Intel Corporation
+
+; The learner tables are very useful for learning and connection tracking.
+;
+; As opposed to regular tables, which are read-only for the data plane, the learner tables can be
+; updated by the data plane without any control plane intervention. The "learning" process typically
+; takes place by having the default action (i.e. the table action which is executed on lookup miss)
+; explicitly add to the table with a specific action the key that just missed the lookup operation.
+; Each table key expires automatically after a configurable timeout period if not hit during this
+; interval.
+;
+; This example demonstrates a simple connection tracking setup, where the connections are identified
+; by the IPv4 destination address. The forwarding action assigned to each new connection gets the
+; output port as argument, with the output port of each connection generated by a counter that is
+; persistent between packets. On top of the usual table stats, the learner table stats include the
+; number of packets with learning related events.
+
+//
+// Headers
+//
+struct ethernet_h {
+	bit<48> dst_addr
+	bit<48> src_addr
+	bit<16> ethertype
+}
+
+struct ipv4_h {
+	bit<8> ver_ihl
+	bit<8> diffserv
+	bit<16> total_len
+	bit<16> identification
+	bit<16> flags_offset
+	bit<8> ttl
+	bit<8> protocol
+	bit<16> hdr_checksum
+	bit<32> src_addr
+	bit<32> dst_addr
+}
+
+header ethernet instanceof ethernet_h
+header ipv4 instanceof ipv4_h
+
+//
+// Meta-data
+//
+struct metadata_t {
+	bit<32> port_in
+	bit<32> port_out
+
+	// Arguments for the "fwd_action" action.
+	bit<32> fwd_action_arg_port_out
+}
+
+metadata instanceof metadata_t
+
+//
+// Registers.
+//
+regarray counter size 1 initval 0
+
+//
+// Actions
+//
+struct fwd_action_args_t {
+	bit<32> port_out
+}
+
+action fwd_action args instanceof fwd_action_args_t {
+	mov m.port_out t.port_out
+	return
+}
+
+action learn_action args none {
+	// Read current counter value into m.fwd_action_arg_port_out.
+	regrd m.fwd_action_arg_port_out counter 0
+
+	// Increment the counter.
+	regadd counter 0 1
+
+	// Limit the output port values to 0 .. 3.
+	and m.fwd_action_arg_port_out 3
+
+	// Add the current lookup key to the table with fwd_action as the key action. The action
+	// arguments are read from the packet meta-data (the m.fwd_action_arg_port_out field). These
+	// packet meta-data fields have to be written before the "learn" instruction is invoked.
+	learn fwd_action
+
+	// Send the current packet to the same output port.
+	mov m.port_out m.fwd_action_arg_port_out
+
+	return
+}
+
+//
+// Tables.
+//
+learner fwd_table {
+	key {
+		h.ipv4.dst_addr
+	}
+
+	actions {
+		fwd_action args m.fwd_action_arg_port_out
+
+		learn_action args none
+	}
+
+	default_action learn_action args none
+
+	size 1048576
+
+	timeout 120
+}
+
+//
+// Pipeline.
+//
+apply {
+	rx m.port_in
+	extract h.ethernet
+	extract h.ipv4
+	table fwd_table
+	emit h.ethernet
+	emit h.ipv4
+	tx m.port_out
+}