From patchwork Fri Sep 17 15:24:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Laatz X-Patchwork-Id: 99219 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D8E38A0C43; Fri, 17 Sep 2021 17:25:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5B99A41189; Fri, 17 Sep 2021 17:25:05 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id CB40A4114A for ; Fri, 17 Sep 2021 17:25:02 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10110"; a="222476016" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="222476016" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 08:25:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="651909819" Received: from silpixa00401122.ir.intel.com ([10.55.128.10]) by orsmga005.jf.intel.com with ESMTP; 17 Sep 2021 08:25:00 -0700 From: Kevin Laatz To: dev@dpdk.org Cc: bruce.richardson@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, conor.walsh@intel.com, Kevin Laatz Date: Fri, 17 Sep 2021 15:24:29 +0000 Message-Id: <20210917152437.3270330-9-kevin.laatz@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917152437.3270330-1-kevin.laatz@intel.com> References: <20210827172048.558704-1-kevin.laatz@intel.com> <20210917152437.3270330-1-kevin.laatz@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 08/16] dma/idxd: add start and stop functions for pci devices X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add device start/stop functions for DSA devices bound to vfio. For devices bound to the IDXD kernel driver, these are not required since the IDXD kernel driver takes care of this. Signed-off-by: Bruce Richardson Signed-off-by: Kevin Laatz Reviewed-by: Conor Walsh --- doc/guides/dmadevs/idxd.rst | 3 +++ drivers/dma/idxd/idxd_pci.c | 52 +++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/doc/guides/dmadevs/idxd.rst b/doc/guides/dmadevs/idxd.rst index abfa5be9ea..a603c5dd22 100644 --- a/doc/guides/dmadevs/idxd.rst +++ b/doc/guides/dmadevs/idxd.rst @@ -150,3 +150,6 @@ The following code shows how the device is configured in :start-after: Setup of the dmadev device. 8< :end-before: >8 End of setup of the dmadev device. :dedent: 1 + +Once configured, the device can then be made ready for use by calling the +``rte_dma_start()`` API. diff --git a/drivers/dma/idxd/idxd_pci.c b/drivers/dma/idxd/idxd_pci.c index 0216ab80d9..cfb64ce220 100644 --- a/drivers/dma/idxd/idxd_pci.c +++ b/drivers/dma/idxd/idxd_pci.c @@ -59,11 +59,63 @@ idxd_is_wq_enabled(struct idxd_dmadev *idxd) return ((state >> WQ_STATE_SHIFT) & WQ_STATE_MASK) == 0x1; } +static int +idxd_pci_dev_stop(struct rte_dma_dev *dev) +{ + struct idxd_dmadev *idxd = dev->dev_private; + uint8_t err_code; + + if (!idxd_is_wq_enabled(idxd)) { + IDXD_PMD_ERR("Work queue %d already disabled", idxd->qid); + return -EALREADY; + } + + err_code = idxd_pci_dev_command(idxd, idxd_disable_wq); + if (err_code || idxd_is_wq_enabled(idxd)) { + IDXD_PMD_ERR("Failed disabling work queue %d, error code: %#x", + idxd->qid, err_code); + return -err_code; + } + IDXD_PMD_DEBUG("Work queue %d disabled OK", idxd->qid); + + return 0; +} + +static int +idxd_pci_dev_start(struct rte_dma_dev *dev) +{ + struct idxd_dmadev *idxd = dev->dev_private; + uint8_t err_code; + + if (idxd_is_wq_enabled(idxd)) { + IDXD_PMD_WARN("WQ %d already enabled", idxd->qid); + return 0; + } + + if (idxd->desc_ring == NULL) { + IDXD_PMD_ERR("WQ %d has not been fully configured", idxd->qid); + return -EINVAL; + } + + err_code = idxd_pci_dev_command(idxd, idxd_enable_wq); + if (err_code || !idxd_is_wq_enabled(idxd)) { + IDXD_PMD_ERR("Failed enabling work queue %d, error code: %#x", + idxd->qid, err_code); + return err_code == 0 ? -1 : err_code; + } + + IDXD_PMD_DEBUG("Work queue %d enabled OK", idxd->qid); + + return 0; +} + static const struct rte_dma_dev_ops idxd_pci_ops = { .dev_dump = idxd_dump, .dev_configure = idxd_configure, .vchan_setup = idxd_vchan_setup, .dev_info_get = idxd_info_get, + .dev_start = idxd_pci_dev_start, + .dev_stop = idxd_pci_dev_stop, }; /* each portal uses 4 x 4k pages */