diff mbox series

common/cnxk: support 98XX CPT dual block

Message ID 20210916113419.16734-1-ktejasree@marvell.com (mailing list archive)
State Accepted
Delegated to: akhil goyal
Headers show
Series common/cnxk: support 98XX CPT dual block | expand

Checks

Context Check Description
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/intel-Testing fail Testing issues
ci/Intel-compilation success Compilation OK
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-spell-check-testing warning Testing issues
ci/github-robot: build success github build: passed
ci/checkpatch success coding style OK

Commit Message

Tejasree Kondoj Sept. 16, 2021, 11:34 a.m. UTC
CN98xx SoC comes up with two CPT blocks wrt
CN96xx, CN93xx, to achieve higher performance.

Adding support to allocate all LFs of VF with even BDF from CPT0
and all LFs of VF with odd BDF from CPT1.
If LFs are not available in one block then they will be allocated
from alternate block.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 doc/guides/rel_notes/release_21_11.rst |  1 +
 drivers/common/cnxk/roc_cpt.c          | 36 ++++++++++++++++++++------
 drivers/common/cnxk/roc_cpt.h          | 10 +++++++
 3 files changed, 39 insertions(+), 8 deletions(-)

Comments

Akhil Goyal Oct. 5, 2021, 2:16 p.m. UTC | #1
> CN98xx SoC comes up with two CPT blocks wrt
> CN96xx, CN93xx, to achieve higher performance.
> 
> Adding support to allocate all LFs of VF with even BDF from CPT0
> and all LFs of VF with odd BDF from CPT1.
> If LFs are not available in one block then they will be allocated
> from alternate block.
> 
> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

Applied to dpdk-next-crypto

Thanks.
diff mbox series

Patch

diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst
index 43d367bcad..1aae9fce7b 100644
--- a/doc/guides/rel_notes/release_21_11.rst
+++ b/doc/guides/rel_notes/release_21_11.rst
@@ -68,6 +68,7 @@  New Features
   * Added Transport mode support in lookaside protocol (IPsec) for CN10K.
   * Added UDP encapsulation support in lookaside protocol (IPsec) for CN10K.
   * Added support for lookaside protocol (IPsec) offload for CN9K.
+  * Added CN98xx dual block support.
 
 * **Added support for event crypto adapter on Marvell CN10K and CN9K.**
 
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 33524ef504..db201b1396 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -367,7 +367,7 @@  cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)
 	if (rc)
 		return -EIO;
 
-	*nb_lf = rsp->cpt;
+	*nb_lf = PLT_MAX((uint16_t)rsp->cpt, (uint16_t)rsp->cpt1);
 	return 0;
 }
 
@@ -401,7 +401,7 @@  cpt_lfs_free(struct dev *dev)
 }
 
 static int
-cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)
+cpt_hardware_caps_get(struct dev *dev, struct roc_cpt *roc_cpt)
 {
 	struct cpt_caps_rsp_msg *rsp;
 	int ret;
@@ -412,7 +412,8 @@  cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)
 	if (ret)
 		return -EIO;
 
-	mbox_memcpy(hw_caps, rsp->eng_caps,
+	roc_cpt->cpt_revision = rsp->cpt_revision;
+	mbox_memcpy(roc_cpt->hw_caps, rsp->eng_caps,
 		    sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);
 
 	return 0;
@@ -472,21 +473,40 @@  int
 roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
 {
 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
-	uint8_t blkaddr = RVU_BLOCK_ADDR_CPT0;
+	uint8_t blkaddr[ROC_CPT_MAX_BLKS];
 	struct msix_offset_rsp *rsp;
 	uint8_t eng_grpmsk;
+	int blknum = 0;
 	int rc, i;
 
+	blkaddr[0] = RVU_BLOCK_ADDR_CPT0;
+	blkaddr[1] = RVU_BLOCK_ADDR_CPT1;
+
+	if ((roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_98XX) &&
+	    (cpt->dev.pf_func & 0x1))
+		blknum = (blknum + 1) % ROC_CPT_MAX_BLKS;
+
 	/* Request LF resources */
-	rc = cpt_lfs_attach(&cpt->dev, blkaddr, true, nb_lf);
-	if (rc)
+	rc = cpt_lfs_attach(&cpt->dev, blkaddr[blknum], true, nb_lf);
+
+	/* Request LFs from another block if current block has less LFs */
+	if (roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_98XX && rc == ENOSPC) {
+		blknum = (blknum + 1) % ROC_CPT_MAX_BLKS;
+		rc = cpt_lfs_attach(&cpt->dev, blkaddr[blknum], true, nb_lf);
+	}
+	if (rc) {
+		plt_err("Could not attach LFs");
 		return rc;
+	}
+
+	for (i = 0; i < nb_lf; i++)
+		cpt->lf_blkaddr[i] = blkaddr[blknum];
 
 	eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
 		     (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
 		     (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
 
-	rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr, false);
+	rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false);
 	if (rc)
 		goto lfs_detach;
 
@@ -617,7 +637,7 @@  roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 	cpt->pci_dev = pci_dev;
 	roc_cpt->lmt_base = dev->lmt_base;
 
-	rc = cpt_hardware_caps_get(dev, roc_cpt->hw_caps);
+	rc = cpt_hardware_caps_get(dev, roc_cpt);
 	if (rc) {
 		plt_err("Could not determine hardware capabilities");
 		goto fail;
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 9e63073a52..38fcd4d399 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -16,6 +16,7 @@ 
 #define ROC_CPT_DFLT_ENG_GRP_AE	   2UL
 
 #define ROC_CPT_MAX_LFS 64
+#define ROC_CPT_MAX_BLKS 2
 #define ROC_CN10K_CPT_INST_DW_M1                                               \
 	((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7))
 #define ROC_CN10K_TWO_CPT_INST_DW_M1                                           \
@@ -76,6 +77,14 @@ 
 #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20
 #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40
 
+enum {
+	ROC_CPT_REVISION_ID_83XX = 0,
+	ROC_CPT_REVISION_ID_96XX_B0 = 1,
+	ROC_CPT_REVISION_ID_96XX_C0 = 2,
+	ROC_CPT_REVISION_ID_98XX = 3,
+	ROC_CPT_REVISION_ID_106XX = 4,
+};
+
 struct roc_cpt_lmtline {
 	uint64_t io_addr;
 	uint64_t *fc_addr;
@@ -111,6 +120,7 @@  struct roc_cpt {
 	/**< CPT device capabilities */
 	union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
 	uint8_t eng_grp[CPT_MAX_ENG_TYPES];
+	uint8_t cpt_revision;
 
 #define ROC_CPT_MEM_SZ (6 * 1024)
 	uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;