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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT007.mail.protection.outlook.com (10.13.174.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4523.14 via Frontend Transport; Wed, 15 Sep 2021 10:44:45 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 10:44:45 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 10:44:42 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Wed, 15 Sep 2021 13:43:44 +0300 Message-ID: <20210915104348.12920-9-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210915104348.12920-1-talshn@nvidia.com> References: <20210915104348.12920-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 035dda00-d592-49c1-9398-08d97835d556 X-MS-TrafficTypeDiagnostic: DM6PR12MB4577: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; 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CAT:NONE; SFS:(4636009)(39860400002)(376002)(136003)(346002)(396003)(46966006)(36840700001)(36860700001)(356005)(70586007)(70206006)(2906002)(8936002)(7696005)(16526019)(82310400003)(2616005)(26005)(8676002)(426003)(336012)(36906005)(186003)(36756003)(7636003)(82740400003)(54906003)(316002)(55016002)(47076005)(1076003)(86362001)(5660300002)(107886003)(478600001)(6286002)(4326008)(6916009); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2021 10:44:45.6468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 035dda00-d592-49c1-9398-08d97835d556 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4577 Subject: [dpdk-dev] [RFC PATCH 08/12] net/mlx5: support TSO offload on Windows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support of the TSO offloading by checking the relevant FW capability for NIC support. Supported offloads: DEV_TX_OFFLOAD_TCP_TSO DEV_TX_OFFLOAD_VXLAN_TNL_TSO DEV_TX_OFFLOAD_GRE_TNL_TSO DEV_TX_OFFLOAD_GENEVE_TNL_TSO Signed-off-by: Tal Shnaiderman --- drivers/net/mlx5/windows/mlx5_os.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index a221ee0501..2aaacd0afb 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -165,6 +165,7 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) device_attr->max_pd = 1 << hca_attr.log_max_pd; device_attr->max_srq = 1 << hca_attr.log_max_srq; device_attr->max_srq_wr = 1 << hca_attr.log_max_srq_sz; + device_attr->max_tso = 1 << hca_attr.max_lso_cap; if (hca_attr.rss_ind_tbl_cap) { device_attr->max_rwq_indirection_table_size = 1 << hca_attr.rss_ind_tbl_cap; @@ -480,6 +481,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); config->hw_padding = 0; } + config->tso = (sh->device_attr.max_tso > 0); if (config->tso) config->tso_max_payload_sz = sh->device_attr.max_tso; DRV_LOG(DEBUG, "%sMPS is %s.",