diff mbox series

[RFC,06/12] net/mlx5: query tunneling support on Windows

Message ID 20210915104348.12920-7-talshn@nvidia.com (mailing list archive)
State RFC
Delegated to: Raslan Darawsheh
Headers show
Series Expand NIC offloads support on Windows | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tal Shnaiderman Sept. 15, 2021, 10:43 a.m. UTC
Query tunneling supported on the NIC.

Save the offloads values in a config parameter.
This is needed for the following TSO support:

DEV_TX_OFFLOAD_VXLAN_TNL_TSO
DEV_TX_OFFLOAD_GRE_TNL_TSO
DEV_TX_OFFLOAD_GENEVE_TNL_TSO

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
---
 drivers/net/mlx5/mlx5.c            | 14 ++++++++++++++
 drivers/net/mlx5/mlx5.h            |  2 ++
 drivers/net/mlx5/windows/mlx5_os.c |  2 ++
 drivers/net/mlx5/windows/mlx5_os.h |  5 +++++
 4 files changed, 23 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 80fc9e3168..69c98e29be 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -963,6 +963,20 @@  mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 	return sw_parsing_offloads;
 }
 
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
+{
+	uint32_t tn_offloads = 0;
+
+	if (attr->tunnel_stateless_vxlan)
+		tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
+	if (attr->tunnel_stateless_gre)
+		tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
+	if (attr->tunnel_stateless_geneve_rx)
+		tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
+	return tn_offloads;
+}
+
 /*
  * Allocate Rx and Tx UARs in robust fashion.
  * This routine handles the following UAR allocation issues:
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 42688b2dc3..980d3227f2 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1829,5 +1829,7 @@  int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
 			  struct mlx5_aso_ct_action *ct);
 uint32_t
 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
 
 #endif /* RTE_PMD_MLX5_H_ */
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 1e258e044e..a221ee0501 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -171,6 +171,8 @@  mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
 	}
 	device_attr->sw_parsing_offloads =
 		mlx5_get_supported_sw_parsing_offloads(&hca_attr);
+	device_attr->tunnel_offloads_caps =
+		mlx5_get_supported_tunneling_offloads(&hca_attr);
 	pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
 	if (pv_iseg == NULL) {
 		DRV_LOG(ERR, "Failed to get device hca_iseg");
diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h
index 6de683357c..f145088176 100644
--- a/drivers/net/mlx5/windows/mlx5_os.h
+++ b/drivers/net/mlx5/windows/mlx5_os.h
@@ -22,4 +22,9 @@  enum mlx5_sw_parsing_offloads {
 	MLX5_SW_PARSING_TSO_CAP =  1 << 2,
 };
 
+enum mlx5_tunnel_offloads {
+	MLX5_TUNNELED_OFFLOADS_VXLAN_CAP  = 1 << 0,
+	MLX5_TUNNELED_OFFLOADS_GRE_CAP	  = 1 << 1,
+	MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2,
+};
 #endif /* RTE_PMD_MLX5_OS_H_ */