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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT024.mail.protection.outlook.com (10.13.174.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4523.14 via Frontend Transport; Wed, 15 Sep 2021 10:44:35 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 10:44:34 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 10:44:31 +0000 From: Tal Shnaiderman To: CC: , , , , , , , , Date: Wed, 15 Sep 2021 13:43:40 +0300 Message-ID: <20210915104348.12920-5-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210915104348.12920-1-talshn@nvidia.com> References: <20210915104348.12920-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7c1419e9-1fb0-498d-94aa-08d97835cf34 X-MS-TrafficTypeDiagnostic: CH0PR12MB5372: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3631; 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CAT:NONE; SFS:(4636009)(39860400002)(376002)(136003)(346002)(396003)(46966006)(36840700001)(36860700001)(356005)(70586007)(70206006)(2906002)(6666004)(83380400001)(8936002)(7696005)(16526019)(82310400003)(2616005)(26005)(8676002)(426003)(336012)(36906005)(186003)(36756003)(7636003)(82740400003)(54906003)(316002)(55016002)(47076005)(1076003)(86362001)(5660300002)(478600001)(6286002)(4326008)(6916009); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2021 10:44:35.3585 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7c1419e9-1fb0-498d-94aa-08d97835cf34 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5372 Subject: [dpdk-dev] [RFC PATCH 04/12] net/mlx5: fix tunneling support query X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the PMD decides if the tunneling offload can enable VXLAN/GRE/GENEVE tunneled TSO support by checking config->tunnel_en (single bit) and config->tso. This is incorrect, the right way is to check the following flags returned by the mlx5dv_query_device function: MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload DEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled. MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload DEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled. MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload DEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled. The fix enables the offloads according to the correct flags returned by the kernel. Fixes: dbccb4cddcd2f7c ("net/mlx5: convert to new Tx offloads API") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman --- drivers/net/mlx5/linux/mlx5_os.c | 6 ++---- drivers/net/mlx5/linux/mlx5_os.h | 15 +++++++++++++++ drivers/net/mlx5/mlx5.h | 2 +- drivers/net/mlx5/mlx5_txq.c | 24 +++++++++++++++++++----- 4 files changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 536b39ba9c..585e880f3c 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -963,7 +963,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, int err = 0; unsigned int hw_padding = 0; unsigned int mps; - unsigned int tunnel_en = 0; unsigned int mpls_en = 0; unsigned int swp = 0; unsigned int mprq = 0; @@ -1145,7 +1144,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->cqe_comp = 1; #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { - tunnel_en = ((dv_attr.tunnel_offloads_caps & + config->tunnel_en = ((dv_attr.tunnel_offloads_caps & MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && (dv_attr.tunnel_offloads_caps & MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && @@ -1153,12 +1152,11 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); } DRV_LOG(DEBUG, "tunnel offloading is %ssupported", - tunnel_en ? "" : "not "); + config->tunnel_en ? "" : "not "); #else DRV_LOG(WARNING, "tunnel offloading disabled due to old OFED/rdma-core version"); #endif - config->tunnel_en = tunnel_en; #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT mpls_en = ((dv_attr.tunnel_offloads_caps & MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h index da036edb72..80c70d713a 100644 --- a/drivers/net/mlx5/linux/mlx5_os.h +++ b/drivers/net/mlx5/linux/mlx5_os.h @@ -33,4 +33,19 @@ enum mlx5_sw_parsing_offloads { MLX5_SW_PARSING_TSO_CAP = 0, #endif }; + +enum mlx5_tunnel_offloads { +#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN, + MLX5_TUNNELED_OFFLOADS_GRE_CAP = + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE, + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE, +#else + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 0, + MLX5_TUNNELED_OFFLOADS_GRE_CAP = 0, + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0, +#endif +}; #endif /* RTE_PMD_MLX5_OS_H_ */ diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 45713d1709..42688b2dc3 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -244,7 +244,7 @@ struct mlx5_dev_config { unsigned int hw_padding:1; /* End alignment padding is supported. */ unsigned int vf:1; /* This is a VF. */ unsigned int sf:1; /* This is a SF. */ - unsigned int tunnel_en:1; + unsigned int tunnel_en:3; /* Whether tunnel stateless offloads are supported. */ unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ unsigned int cqe_comp:1; /* CQE compression is enabled. */ diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index 8dca2b7f79..54f42292ac 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -120,10 +120,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev) if (config->tunnel_en) { if (config->hw_csum) offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; - if (config->tso) - offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | - DEV_TX_OFFLOAD_GRE_TNL_TSO | - DEV_TX_OFFLOAD_GENEVE_TNL_TSO); + if (config->tso) { + if (config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP) + offloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO; + if (config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_GRE_CAP) + offloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO; + if (config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP) + offloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO; + } } if (!config->mprq.enabled) offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE; @@ -978,7 +985,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl) MLX5_MAX_TSO_HEADER); txq_ctrl->txq.tso_en = 1; } - txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp; + if (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) && + (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) | + ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) && + (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) | + ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) && + (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) | + (config->swp & MLX5_SW_PARSING_TSO_CAP)) + txq_ctrl->txq.tunnel_en = 1; txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO | DEV_TX_OFFLOAD_UDP_TNL_TSO) & txq_ctrl->txq.offloads) && (config->swp &