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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by BN8NAM11FT055.mail.protection.outlook.com (10.13.177.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4523.14 via Frontend Transport; Wed, 15 Sep 2021 10:44:36 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 03:44:31 -0700 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 10:44:29 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Wed, 15 Sep 2021 13:43:39 +0300 Message-ID: <20210915104348.12920-4-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210915104348.12920-1-talshn@nvidia.com> References: <20210915104348.12920-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 58f6aefb-2389-4a18-553c-08d97835d01c X-MS-TrafficTypeDiagnostic: BL1PR12MB5048: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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CAT:NONE; SFS:(4636009)(396003)(39860400002)(376002)(136003)(346002)(46966006)(36840700001)(426003)(5660300002)(36860700001)(83380400001)(86362001)(8676002)(55016002)(4326008)(6666004)(2616005)(7696005)(70206006)(70586007)(47076005)(54906003)(336012)(316002)(82310400003)(36756003)(6286002)(26005)(6916009)(7636003)(2906002)(107886003)(16526019)(1076003)(82740400003)(186003)(356005)(8936002)(478600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2021 10:44:36.7864 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58f6aefb-2389-4a18-553c-08d97835d01c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5048 Subject: [dpdk-dev] [RFC PATCH 03/12] net/mlx5: query software parsing support on Windows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Query software parsing supported on the NIC. Save the offloads values in a config parameter. This is needed for the outer IPv4 checksum and IP and UPD tunneled packet TSO support. Signed-off-by: Tal Shnaiderman --- drivers/net/mlx5/mlx5.c | 16 ++++++++++++++++ drivers/net/mlx5/mlx5.h | 2 ++ drivers/net/mlx5/windows/mlx5_os.c | 6 +++++- drivers/net/mlx5/windows/mlx5_os.h | 6 ++++++ 4 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index f84e061fe7..80fc9e3168 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -947,6 +947,22 @@ mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) prf->obj = NULL; } +uint32_t +mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) +{ + uint32_t sw_parsing_offloads = 0; + + if (attr->swp) { + sw_parsing_offloads |= MLX5_SW_PARSING_CAP; + if (attr->swp_csum) + sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP; + + if (attr->swp_lso) + sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP; + } + return sw_parsing_offloads; +} + /* * Allocate Rx and Tx UARs in robust fashion. * This routine handles the following UAR allocation issues: diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index a56f39cd5f..45713d1709 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1827,5 +1827,7 @@ int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, struct rte_flow_action_conntrack *profile); int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, struct mlx5_aso_ct_action *ct); +uint32_t +mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr); #endif /* RTE_PMD_MLX5_H_ */ diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 26fa927039..1e258e044e 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -169,6 +169,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) device_attr->max_rwq_indirection_table_size = 1 << hca_attr.rss_ind_tbl_cap; } + device_attr->sw_parsing_offloads = + mlx5_get_supported_sw_parsing_offloads(&hca_attr); pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg); if (pv_iseg == NULL) { DRV_LOG(ERR, "Failed to get device hca_iseg"); @@ -393,7 +395,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } DRV_LOG(DEBUG, "MPW isn't supported"); mlx5_os_get_dev_attr(sh->ctx, &device_attr); - config->swp = 0; + config->swp = device_attr.sw_parsing_offloads & + (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | + MLX5_SW_PARSING_TSO_CAP); config->ind_table_max_size = sh->device_attr.max_rwq_indirection_table_size; cqe_comp = 0; diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h index 7fe41d4e90..6de683357c 100644 --- a/drivers/net/mlx5/windows/mlx5_os.h +++ b/drivers/net/mlx5/windows/mlx5_os.h @@ -16,4 +16,10 @@ enum { #define MLX5_NAMESIZE MLX5_FS_NAME_MAX +enum mlx5_sw_parsing_offloads { + MLX5_SW_PARSING_CAP = 1 << 0, + MLX5_SW_PARSING_CSUM_CAP = 1 << 1, + MLX5_SW_PARSING_TSO_CAP = 1 << 2, +}; + #endif /* RTE_PMD_MLX5_OS_H_ */