diff mbox series

[RFC,02/12] common/mlx5: read software parsing capabilities from DevX

Message ID 20210915104348.12920-3-talshn@nvidia.com (mailing list archive)
State RFC, archived
Delegated to: Raslan Darawsheh
Headers
Series Expand NIC offloads support on Windows |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tal Shnaiderman Sept. 15, 2021, 10:43 a.m. UTC 
  mlx5 in Windows needs the software parsing hca capabilities
to query the NIC for TSO and Checksum offloading support.

Added the capability as part of the capabilities
queried by the PMD using DevX.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++
 drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++
 2 files changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 56407cc332..70ba74e112 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -991,6 +991,12 @@  mlx5_devx_cmd_query_hca_attr(void *ctx,
 					hcattr, tunnel_lro_gre);
 	attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 					  hcattr, tunnel_lro_vxlan);
+	attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
+					  hcattr, swp);
+	attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
+					  hcattr, swp_csum);
+	attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
+					  hcattr, swp_lso);
 	attr->lro_max_msg_sz_mode = MLX5_GET
 					(per_protocol_networking_offload_caps,
 					 hcattr, lro_max_msg_sz_mode);
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index e576e30f24..caa444bc15 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -116,6 +116,9 @@  struct mlx5_hca_attr {
 	uint32_t lro_cap:1;
 	uint32_t tunnel_lro_gre:1;
 	uint32_t tunnel_lro_vxlan:1;
+	uint32_t swp:1;
+	uint32_t swp_csum:1;
+	uint32_t swp_lso:1;
 	uint32_t lro_max_msg_sz_mode:2;
 	uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
 	uint16_t lro_min_mss_size;