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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by CO1NAM11FT028.mail.protection.outlook.com (10.13.175.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4523.14 via Frontend Transport; Wed, 15 Sep 2021 10:44:27 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 10:44:26 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep 2021 10:44:23 +0000 From: Tal Shnaiderman To: CC: , , , , , , , , Date: Wed, 15 Sep 2021 13:43:37 +0300 Message-ID: <20210915104348.12920-2-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210915104348.12920-1-talshn@nvidia.com> References: <20210915104348.12920-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c134fa94-3aa3-4974-0b48-08d97835ca46 X-MS-TrafficTypeDiagnostic: MWHPR12MB1405: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1824; 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CAT:NONE; SFS:(4636009)(136003)(396003)(376002)(346002)(39860400002)(36840700001)(46966006)(36756003)(36860700001)(426003)(4326008)(8676002)(8936002)(82740400003)(316002)(7636003)(356005)(70586007)(5660300002)(70206006)(54906003)(2906002)(55016002)(1076003)(86362001)(6286002)(7696005)(6916009)(186003)(82310400003)(16526019)(26005)(336012)(47076005)(83380400001)(36906005)(2616005)(478600001)(6666004)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2021 10:44:27.0634 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c134fa94-3aa3-4974-0b48-08d97835ca46 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1405 Subject: [dpdk-dev] [RFC PATCH 01/12] net/mlx5: fix software parsing support query X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the PMD decides if the software parsing offload can enable outer IPv4 checksum and tunneled TSO support by checking config->hw_csum and config->tso respectively. This is incorrect, the right way is to check the following flags returned by the mlx5dv_query_device function: MLX5DV_SW_PARSING - check general swp support. MLX5DV_SW_PARSING_CSUM - check swp checksum support. MLX5DV_SW_PARSING_LSO - check swp LSO/TSO support. The fix enables the offloads according to the correct flags returned by the kernel. Fixes: e46821e9fcdc60 ("net/mlx5: separate generic tunnel TSO from the standard one") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman --- drivers/net/mlx5/linux/mlx5_os.c | 3 ++- drivers/net/mlx5/linux/mlx5_os.h | 12 ++++++++++++ drivers/net/mlx5/mlx5.h | 2 +- drivers/net/mlx5/mlx5_txq.c | 15 +++++++++------ 4 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 470b16cb9a..536b39ba9c 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1112,7 +1112,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; DRV_LOG(DEBUG, "SWP support: %u", swp); #endif - config->swp = !!swp; + config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP | + MLX5_SW_PARSING_TSO_CAP); #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { struct mlx5dv_striding_rq_caps mprq_caps = diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h index 2991d37df2..da036edb72 100644 --- a/drivers/net/mlx5/linux/mlx5_os.h +++ b/drivers/net/mlx5/linux/mlx5_os.h @@ -21,4 +21,16 @@ enum { int mlx5_auxiliary_get_ifindex(const char *sf_name); + +enum mlx5_sw_parsing_offloads { +#ifdef HAVE_IBV_MLX5_MOD_SWP + MLX5_SW_PARSING_CAP = MLX5DV_SW_PARSING, + MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM, + MLX5_SW_PARSING_TSO_CAP = MLX5DV_SW_PARSING_LSO, +#else + MLX5_SW_PARSING_CAP = 0, + MLX5_SW_PARSING_CSUM_CAP = 0, + MLX5_SW_PARSING_TSO_CAP = 0, +#endif +}; #endif /* RTE_PMD_MLX5_OS_H_ */ diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index e02714e231..a56f39cd5f 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -260,7 +260,7 @@ struct mlx5_dev_config { unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ unsigned int lacp_by_user:1; /* Enable user to manage LACP traffic. */ - unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ + unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */ unsigned int devx:1; /* Whether devx interface is available or not. */ unsigned int dest_tir:1; /* Whether advanced DR API is available. */ unsigned int reclaim_mode:2; /* Memory reclaim mode. */ diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index eb4d34ca55..8dca2b7f79 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -111,9 +111,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev) if (config->tx_pp) offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP; if (config->swp) { - if (config->hw_csum) + if (config->swp & MLX5_SW_PARSING_CSUM_CAP) offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; - if (config->tso) + if (config->swp & MLX5_SW_PARSING_TSO_CAP) offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO | DEV_TX_OFFLOAD_UDP_TNL_TSO); } @@ -979,10 +979,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl) txq_ctrl->txq.tso_en = 1; } txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp; - txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO | - DEV_TX_OFFLOAD_UDP_TNL_TSO | - DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) & - txq_ctrl->txq.offloads) && config->swp; + txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO | + DEV_TX_OFFLOAD_UDP_TNL_TSO) & + txq_ctrl->txq.offloads) && (config->swp & + MLX5_SW_PARSING_TSO_CAP)) | + ((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM & + txq_ctrl->txq.offloads) && (config->swp & + MLX5_SW_PARSING_CSUM_CAP)); } /**