diff mbox series

[RFC,01/12] net/mlx5: fix software parsing support query

Message ID 20210915104348.12920-2-talshn@nvidia.com (mailing list archive)
State RFC
Delegated to: Raslan Darawsheh
Headers show
Series Expand NIC offloads support on Windows | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tal Shnaiderman Sept. 15, 2021, 10:43 a.m. UTC
Currently, the PMD decides if the software parsing
offload can enable outer IPv4 checksum and tunneled
TSO support by checking config->hw_csum and config->tso
respectively.

This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:

MLX5DV_SW_PARSING - check general swp support.
MLX5DV_SW_PARSING_CSUM - check swp checksum support.
MLX5DV_SW_PARSING_LSO - check swp LSO/TSO support.

The fix enables the offloads according to the correct
flags returned by the kernel.

Fixes: e46821e9fcdc60 ("net/mlx5: separate generic tunnel TSO from the standard one")
Cc: stable@dpdk.org

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
---
 drivers/net/mlx5/linux/mlx5_os.c |  3 ++-
 drivers/net/mlx5/linux/mlx5_os.h | 12 ++++++++++++
 drivers/net/mlx5/mlx5.h          |  2 +-
 drivers/net/mlx5/mlx5_txq.c      | 15 +++++++++------
 4 files changed, 24 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 470b16cb9a..536b39ba9c 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1112,7 +1112,8 @@  mlx5_dev_spawn(struct rte_device *dpdk_dev,
 		swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
 	DRV_LOG(DEBUG, "SWP support: %u", swp);
 #endif
-	config->swp = !!swp;
+	config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
+		MLX5_SW_PARSING_TSO_CAP);
 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 	if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
 		struct mlx5dv_striding_rq_caps mprq_caps =
diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index 2991d37df2..da036edb72 100644
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -21,4 +21,16 @@  enum {
 
 int mlx5_auxiliary_get_ifindex(const char *sf_name);
 
+
+enum mlx5_sw_parsing_offloads {
+#ifdef HAVE_IBV_MLX5_MOD_SWP
+	MLX5_SW_PARSING_CAP      = MLX5DV_SW_PARSING,
+	MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM,
+	MLX5_SW_PARSING_TSO_CAP  = MLX5DV_SW_PARSING_LSO,
+#else
+	MLX5_SW_PARSING_CAP      = 0,
+	MLX5_SW_PARSING_CSUM_CAP = 0,
+	MLX5_SW_PARSING_TSO_CAP  = 0,
+#endif
+};
 #endif /* RTE_PMD_MLX5_OS_H_ */
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index e02714e231..a56f39cd5f 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -260,7 +260,7 @@  struct mlx5_dev_config {
 	unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
 	unsigned int lacp_by_user:1;
 	/* Enable user to manage LACP traffic. */
-	unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
+	unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
 	unsigned int devx:1; /* Whether devx interface is available or not. */
 	unsigned int dest_tir:1; /* Whether advanced DR API is available. */
 	unsigned int reclaim_mode:2; /* Memory reclaim mode. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index eb4d34ca55..8dca2b7f79 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -111,9 +111,9 @@  mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
 	if (config->tx_pp)
 		offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
 	if (config->swp) {
-		if (config->hw_csum)
+		if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
 			offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-		if (config->tso)
+		if (config->swp & MLX5_SW_PARSING_TSO_CAP)
 			offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
 				     DEV_TX_OFFLOAD_UDP_TNL_TSO);
 	}
@@ -979,10 +979,13 @@  txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
 		txq_ctrl->txq.tso_en = 1;
 	}
 	txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
-	txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
-				 DEV_TX_OFFLOAD_UDP_TNL_TSO |
-				 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
-				txq_ctrl->txq.offloads) && config->swp;
+	txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
+				  DEV_TX_OFFLOAD_UDP_TNL_TSO) &
+				  txq_ctrl->txq.offloads) && (config->swp &
+				  MLX5_SW_PARSING_TSO_CAP)) |
+				((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &
+				 txq_ctrl->txq.offloads) && (config->swp &
+				 MLX5_SW_PARSING_CSUM_CAP));
 }
 
 /**