From patchwork Wed Sep 15 06:11:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 98884 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08597A0C43; Wed, 15 Sep 2021 08:11:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09ED1410E5; Wed, 15 Sep 2021 08:11:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 20BDC410E0 for ; Wed, 15 Sep 2021 08:11:27 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18EJRFXS024750; Tue, 14 Sep 2021 23:11:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=IpeFzG5TUbWGEVvPx2Zx6av5aGE+m98uHBrNTb2Ye9U=; b=b8dLKbZw0t/mEbTp6XDYU5CH4pMS1vLJwwkRkc/VjG7CcOVejrv1t1CdV0TbRaLqKY9+ Yi0c5FNdjocb+1o+lueTPbwrt5zyzrJbEq+bPILvjZ53qH5DU228cTlTegxyVmPpv2pv FH+hXhIU3vqHv7gmVEkAgvEYYoVsME+XlkGliQtZXRLu7ITQyqgl2/l077Pz36OIBlNn iS7b19ua0l8ZVrVoABSusO9PKmfe7pH0qQfJhQsfOdh3pSPSbsmAus2QiHErQRIse7Ik i46t+TrHZmT9focnKI3lRxeeE3IgMOwZoY+XistW2wYa71JrXjg+PR/syQveHokks6aY Ag== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3b2t41m0b5-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 14 Sep 2021 23:11:25 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 23:11:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 14 Sep 2021 23:11:23 -0700 Received: from vvelumuri_asim.marvell.com (unknown [10.29.53.48]) by maili.marvell.com (Postfix) with ESMTP id 4EE363F705B; Tue, 14 Sep 2021 23:11:20 -0700 (PDT) From: Vidya Sagar Velumuri To: , , , , , , , , CC: Date: Wed, 15 Sep 2021 06:11:02 +0000 Message-ID: <20210915061103.28375-2-vvelumuri@marvell.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210915061103.28375-1-vvelumuri@marvell.com> References: <20210915061103.28375-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: puufudEQxRAtutKfEFkhusEPAzI0w1GN X-Proofpoint-ORIG-GUID: puufudEQxRAtutKfEFkhusEPAzI0w1GN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-14_10,2021-09-14_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v1 2/3] crypto/cnxk: support for 256 bit key length in ZUC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for 256 bit key length for ZUC in crpto_cn10k PMD. Add support for digest length of 8 and 16 bytes for ZUC with 256 bit key length. Signed-off-by: Vidya Sagar Velumuri diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 3fa8018695..7422bff10a 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -68,6 +68,7 @@ New Features * Added Transport mode support in lookaside protocol (IPsec) for CN10K. * Added UDP encapsulation support in lookaside protocol (IPsec) for CN10K. * Added support for lookaside protocol (IPsec) offload for CN9K. + * Added support for ZUC algorithm with 256 bit key length for CN10K. * **Added support for event crypto adapter on Marvell CN10K and CN9K.** diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index c4f7824332..31893e1d20 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -860,6 +860,38 @@ cpt_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos, *cur_pos += nb_caps; } +static void +cn10k_crypto_caps_update(struct rte_cryptodev_capabilities cnxk_caps[]) +{ + + struct rte_cryptodev_capabilities *caps; + int i = 0; + + while ((caps = &cnxk_caps[i++])->op != RTE_CRYPTO_OP_TYPE_UNDEFINED) { + if ((caps->op == RTE_CRYPTO_OP_TYPE_SYMMETRIC) && + (caps->sym.xform_type == RTE_CRYPTO_SYM_XFORM_CIPHER) && + (caps->sym.cipher.algo == RTE_CRYPTO_CIPHER_ZUC_EEA3)) { + + caps->sym.cipher.key_size.max = 32; + caps->sym.cipher.key_size.increment = 16; + caps->sym.cipher.iv_size.max = 24; + caps->sym.cipher.iv_size.increment = 8; + } + + if ((caps->op == RTE_CRYPTO_OP_TYPE_SYMMETRIC) && + (caps->sym.xform_type == RTE_CRYPTO_SYM_XFORM_AUTH) && + (caps->sym.auth.algo == RTE_CRYPTO_AUTH_ZUC_EIA3)) { + + caps->sym.auth.key_size.max = 32; + caps->sym.auth.key_size.increment = 16; + caps->sym.auth.digest_size.max = 16; + caps->sym.auth.digest_size.increment = 4; + caps->sym.auth.iv_size.max = 24; + caps->sym.auth.iv_size.increment = 8; + } + } +} + static void crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[], union cpt_eng_caps *hw_caps) @@ -876,6 +908,9 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[], cpt_caps_add(cnxk_caps, &cur_pos, caps_null, RTE_DIM(caps_null)); cpt_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end)); + + if (roc_model_is_cn10k()) + cn10k_crypto_caps_update(cnxk_caps); } const struct rte_cryptodev_capabilities * diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index aedc4bc0d8..7959c4c7af 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -980,7 +980,7 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, uint8_t pdcp_alg_type; uint32_t encr_offset, auth_offset; uint32_t encr_data_len, auth_data_len; - int flags, iv_len = 16; + int flags, iv_len; uint64_t offset_ctrl; uint64_t *offset_vaddr; uint8_t *iv_s; @@ -996,6 +996,9 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, cpt_inst_w4.s.opcode_minor = se_ctx->template_w4.s.opcode_minor; if (flags == 0x1) { + iv_s = params->auth_iv_buf; + iv_len = params->auth_iv_len; + /* * Microcode expects offsets in bytes * TODO: Rounding off @@ -1016,9 +1019,10 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, encr_data_len = 0; encr_offset = 0; - - iv_s = params->auth_iv_buf; } else { + iv_s = params->iv_buf; + iv_len = params->cipher_iv_len; + /* EEA3 or UEA2 */ /* * Microcode expects offsets in bytes @@ -1039,8 +1043,6 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, auth_data_len = 0; auth_offset = 0; - - iv_s = params->iv_buf; } if (unlikely((encr_offset >> 16) || (auth_offset >> 8))) { @@ -1719,7 +1721,7 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess) break; case RTE_CRYPTO_CIPHER_ZUC_EEA3: enc_type = ROC_SE_ZUC_EEA3; - cipher_key_len = 16; + cipher_key_len = c_form->key.length; zsk_flag = ROC_SE_ZS_EA; break; case RTE_CRYPTO_CIPHER_AES_XTS: @@ -2069,6 +2071,9 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, uint32_t iv_buf[4]; int ret; + fc_params.cipher_iv_len = sess->iv_length; + fc_params.auth_iv_len = sess->auth_iv_length; + if (likely(sess->iv_length)) { flags |= ROC_SE_VALID_IV_BUF; fc_params.iv_buf = rte_crypto_op_ctod_offset(cop, uint8_t *, @@ -2379,6 +2384,7 @@ fill_digest_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, */ d_offs = auth_range_off; auth_range_off = 0; + params.auth_iv_len = sess->auth_iv_length; params.auth_iv_buf = rte_crypto_op_ctod_offset( cop, uint8_t *, sess->auth_iv_offset); if (sess->zsk_flag == ROC_SE_K_F9) {