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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT056.mail.protection.outlook.com (10.13.173.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:05 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:05 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:02 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:28 +0300 Message-ID: <20210914053833.7760-6-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bd1f6933-e2eb-42d7-101e-08d977421b49 X-MS-TrafficTypeDiagnostic: PH0PR12MB5402: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(36860700001)(6916009)(86362001)(54906003)(47076005)(508600001)(2616005)(107886003)(83380400001)(70206006)(5660300002)(1076003)(336012)(70586007)(26005)(186003)(16526019)(426003)(7696005)(55016002)(8676002)(6286002)(316002)(36756003)(36906005)(8936002)(82310400003)(7636003)(6666004)(2906002)(356005)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:05.7796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd1f6933-e2eb-42d7-101e-08d977421b49 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5402 Subject: [dpdk-dev] [RFC PATCH 05/10] crypto/mlx5: replace UNIX functions with EAL functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Use the OS agnostic EAL function rte_mem_page_size to get page size value instead of the Linux specific implementation. Also remove the usage of PTHREAD_MUTEX_INITIALIZER which is not support in Windows and initialize priv_list_lock in RTE_INIT. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index b3d5200ca3..3dac69f860 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -33,7 +34,7 @@ TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list = TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list); -static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; +static pthread_mutex_t priv_list_lock; int mlx5_crypto_logtype; @@ -700,7 +701,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, attr.pd = priv->pdn; attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar); attr.cqn = qp->cq_obj.cq->id; - attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE)); + attr.log_page_size = rte_log2_u32(rte_mem_page_size()); attr.rq_size = 0; attr.sq_size = RTE_BIT32(log_nb_desc); attr.dbr_umem_valid = 1; @@ -1134,6 +1135,7 @@ static struct mlx5_class_driver mlx5_crypto_driver = { RTE_INIT(rte_mlx5_crypto_init) { + pthread_mutex_init(&priv_list_lock, NULL); mlx5_common_init(); if (mlx5_glue != NULL) mlx5_class_driver_register(&mlx5_crypto_driver);