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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT016.mail.protection.outlook.com (10.13.173.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:04 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 13 Sep 2021 22:40:02 -0700 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:00 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:27 +0300 Message-ID: <20210914053833.7760-5-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ddc97aa1-3c53-4445-b482-08d977421a73 X-MS-TrafficTypeDiagnostic: BYAPR12MB3191: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(8676002)(6666004)(356005)(82310400003)(54906003)(336012)(4326008)(426003)(8936002)(7636003)(5660300002)(16526019)(186003)(47076005)(6286002)(508600001)(83380400001)(55016002)(316002)(26005)(6916009)(2906002)(70586007)(70206006)(2616005)(1076003)(7696005)(107886003)(36756003)(86362001)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:04.2124 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddc97aa1-3c53-4445-b482-08d977421a73 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3191 Subject: [dpdk-dev] [RFC PATCH 04/10] common/mlx5: add memory region OS agnostic functions for Linux X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The OS agnostic functions for memory region registration/deregistration (mlx5_os_reg_mr mlx5_os_dereg_mr) exist only for Windows OS. Adding them for Linux as well as they are needed for memory region activities in shared code. Signed-off-by: Tal Shnaiderman --- drivers/common/mlx5/linux/mlx5_common_os.c | 35 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_common.h | 9 +++++++ drivers/common/mlx5/windows/mlx5_common_os.c | 2 +- drivers/common/mlx5/windows/mlx5_common_os.h | 6 ----- 4 files changed, 45 insertions(+), 7 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index 4aada82669..fd0ec6b748 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -491,3 +491,38 @@ mlx5_os_get_pdn(void *pd, uint32_t *pdn) return -ENOTSUP; #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ } + +/** + * Register mr. Given protection domain pointer, pointer to addr and length + * register the memory region. + * + * @param[in] pd + * Pointer to protection domain context (type mlx5_pd). + * @param[in] addr + * Pointer to memory start address (type devx_device_ctx). + * @param[in] length + * Lengtoh of the memory to register. + * @param[out] pmd_mr + * pmd_mr struct set with lkey, address, length, pointer to mr object, mkey + * + * @return + * 0 on successful registration, -1 otherwise + */ +int +mlx5_os_reg_mr(void *pd, + void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr) +{ + return mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr); +} + +/** + * De-register mr. + * + * @param[in] pmd_mr + * Pointer to PMD mr object + */ +void +mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr) +{ + mlx5_common_verbs_dereg_mr(pmd_mr); +} diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index fcdf376193..a87318db91 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -21,6 +21,7 @@ #include "mlx5_prm.h" #include "mlx5_devx_cmds.h" +#include "mlx5_common_mr.h" #include "mlx5_common_os.h" /* Reported driver name. */ @@ -427,4 +428,12 @@ __rte_internal int mlx5_os_get_pdn(void *pd, uint32_t *pdn); +__rte_internal +int +mlx5_os_reg_mr(void *pd, + void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr); +__rte_internal +void +mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr); + #endif /* RTE_PMD_MLX5_COMMON_H_ */ diff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c index 5c9cccd3e9..2ecdf78310 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.c +++ b/drivers/common/mlx5/windows/mlx5_common_os.c @@ -134,7 +134,7 @@ mlx5_os_umem_dereg(void *pumem) } /** - * Register mr. Given protection doamin pointer, pointer to addr and length + * Register mr. Given protection domain pointer, pointer to addr and length * register the memory region. * * @param[in] pd diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index c3d74d3b67..62bdcb40cd 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -13,7 +13,6 @@ #include "mlx5_autoconf.h" #include "mlx5_glue.h" #include "mlx5_malloc.h" -#include "mlx5_common_mr.h" #include "mlx5_win_ext.h" #define MLX5_BF_OFFSET 0x800 @@ -256,11 +255,6 @@ __rte_internal void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access); __rte_internal int mlx5_os_umem_dereg(void *pumem); -__rte_internal -int mlx5_os_reg_mr(void *pd, - void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr); -__rte_internal -void mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr); int mlx5_os_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf, struct rte_pci_addr *addr); #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */