diff mbox series

crypto/mlx5: fix crypto QP indexing

Message ID 20210913140224.18788-1-talshn@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series crypto/mlx5: fix crypto QP indexing |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/github-robot: build success github build: passed
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS

Commit Message

Tal Shnaiderman Sept. 13, 2021, 2:02 p.m. UTC 
  The crypto QP consumer (ci) and producer (pi) indexes are increased
with each successful enqueue/dequeue operations.

However the QP pi index is calculated with a wraparound the number
of elements while the QP ci does not.

This is causing incorrect engine calculation for encqueued WQ values
(wq->pi - wq->ci) and eventually the device stops accepting new enqueue
operations.

Fixed by removing the wraparound on QP pi and using a temp calculation
where wraparound values are needed.

Fixes: 8e196c08ab53 ("crypto/mlx5: support enqueue/dequeue operations")
Cc: stable@dpdk.org

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/crypto/mlx5/mlx5_crypto.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Akhil Goyal Sept. 24, 2021, 5:47 p.m. UTC | #1 
> The crypto QP consumer (ci) and producer (pi) indexes are increased
> with each successful enqueue/dequeue operations.
> 
> However the QP pi index is calculated with a wraparound the number
> of elements while the QP ci does not.
> 
> This is causing incorrect engine calculation for encqueued WQ values
> (wq->pi - wq->ci) and eventually the device stops accepting new enqueue
> operations.
> 
> Fixed by removing the wraparound on QP pi and using a temp calculation
> where wraparound values are needed.
> 
> Fixes: 8e196c08ab53 ("crypto/mlx5: support enqueue/dequeue operations")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
Applied to dpdk-next-crypto
diff mbox series

Patch

diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index b3d5200ca3..eeec554e6e 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -494,6 +494,7 @@  mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
 	struct rte_crypto_op *op;
 	uint16_t mask = qp->entries_n - 1;
 	uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
+	uint32_t idx;
 
 	if (remain < nb_ops)
 		nb_ops = remain;
@@ -502,8 +503,9 @@  mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
 	if (unlikely(remain == 0))
 		return 0;
 	do {
+		idx = qp->pi & mask;
 		op = *ops++;
-		umr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi);
+		umr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * idx);
 		if (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) {
 			qp->stats.enqueue_err_count++;
 			if (remain != nb_ops) {
@@ -512,8 +514,8 @@  mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
 			}
 			return 0;
 		}
-		qp->ops[qp->pi] = op;
-		qp->pi = (qp->pi + 1) & mask;
+		qp->ops[idx] = op;
+		qp->pi++;
 	} while (--remain);
 	qp->stats.enqueued_count += nb_ops;
 	rte_io_wmb();