From patchwork Fri Sep 3 14:21:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 97945 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DEAD5A0C54; Fri, 3 Sep 2021 16:22:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EB93B41139; Fri, 3 Sep 2021 16:22:20 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2058.outbound.protection.outlook.com [40.107.220.58]) by mails.dpdk.org (Postfix) with ESMTP id 2E62B410DD for ; Fri, 3 Sep 2021 16:22:18 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ENvIQ8z25GDhbEwJ/3JBIUTJ5ymPkZnTKJkKY8cO4pzEibl3UYhVHhmyCZ9zK5EHAFYCkk2IYTn8eB9HAAPuoH5bvmY882qvTqn+hWuCCEDAz69LDu1P4AjbsT4h0X1KS2g84ogFgoZ6P4fErGvx936ZDL3kvlK9iwULZHkWpt/4ckcMTZpnSLNC88HIJA8FdSAC4LyNasH6jRhRndKIildrYjRqLilKr/fzy+XKGO0MszIbJMe8Um97oXymBxWLkamebxIPJtZfuT7sLDUcGuSwv7Xe7dWGz0DNYVBYYNsvegQBk638qajyjWVmy9Nkq/YqWIYk7NTi9vtotvCAUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=3seCO/2SOWutXd57H14h2W1GD8HJmJJM6bT/P/Xbi9Q=; b=Yo2KmERI+jVKFuf97/llKmFPyRX5m/JTR+LTwsHrhcG1eT6WMx2thSCjLv3J1EK8BQ/DQ+5YEngUX/rr9acWZgf3YgxJDPPTpBmLQ5MbahJ8YgUlgoSqVlIjgZF7UYZN79Jcb8UDFvRjv1ypbYQ0/loYvggfJQ4EIJT7U49jEBJ4Ls0WR9OLDR98n13qzi+TtbvogEyGmYubOFkvjOZ+aOZGxXeR5kfcwMzmjJRjvEfCLoyTqjZ1nhV5jI/mY7VSBoMG/5Xz4TU8ej5IfFDoK9Kz+7q43q1iSYh4flC7Gm6LrAN+I5OmqV3pRSA7Ibn9jxonoZV53g/9mUJ67F7myg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3seCO/2SOWutXd57H14h2W1GD8HJmJJM6bT/P/Xbi9Q=; b=I1Wlw7SjMOKfJbciyEpIECMmQv88fNeG+9ltFy6f0fdLxeekBTPHLwnUi9pYj2hhZz6dmhCN3lrkPyEY7W/g/vyvEhcXqEpsQpldYRDIca918sm9WcrpsS2Ar2G9Uc/GuOxuT+LdCb3yX/4wRvjzA4ZOEKqHe/v8TG3rLP6XRRuv6/M+lpwpQ7iHYXMzhlBHD3Jto0rt0idAKVVwUGM9wqWeGStNbraAhc5tqCMBLp3vjTuvas3OZtQDtHk45+4o6hzs6tAnl3JIHOWwvMWZZZ7dpsSuI1bWubaZQ6TJY8dH+8O/UxBHm62i6UJTh+3wUiRDXbqUSu/0l5B/OJexpA== Received: from DM3PR12CA0100.namprd12.prod.outlook.com (2603:10b6:0:55::20) by BY5PR12MB3969.namprd12.prod.outlook.com (2603:10b6:a03:195::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.21; Fri, 3 Sep 2021 14:22:16 +0000 Received: from DM6NAM11FT054.eop-nam11.prod.protection.outlook.com (2603:10b6:0:55:cafe::e0) by DM3PR12CA0100.outlook.office365.com (2603:10b6:0:55::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.19 via Frontend Transport; Fri, 3 Sep 2021 14:22:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT054.mail.protection.outlook.com (10.13.173.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4478.19 via Frontend Transport; Fri, 3 Sep 2021 14:22:16 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 3 Sep 2021 14:22:14 +0000 From: Raja Zidane To: Date: Fri, 3 Sep 2021 14:21:54 +0000 Message-ID: <20210903142157.25617-3-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210903142157.25617-1-rzidane@nvidia.com> References: <20210903142157.25617-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ae3892d4-aa4c-42b9-a6e7-08d96ee63b17 X-MS-TrafficTypeDiagnostic: BY5PR12MB3969: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:751; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2OX64OJJ8e1SKKKMO2jmeL6bsna8y33+DFTSdJd5V4MzpUXmtDcR4KdKR3Edz68djtEr+nGnLapOZG/5oXZLz80sOqYgvlEx6Q/jENci65jgimJ5rOe3qw0TZcjpKyuXKJ6k6CeKFkY6jM7cZLjsbAenlrtH6dCseXrrkvnFONJrocGihNTPOfJb+y467SA0UJIdrQ4xZuOSVFAvtTdSb65mlPF7qSX5iq16wKDOTzoKAJWMRCAY8XxHcLK7XD695m9cHFpGkMzgPe2/zWLCYPQAyZIZVCgQQ9+3JS9ZT5QGszaVMAmHXrVLn+dxuj3LVtVwr251blJpDsnx0P7ndrPBRzIep4GxKlKGteeut6KFaHASRrvdayjHb/IMAKn/s+p4MKws+DrqsXi/wGDXADzm22zgrtF93IcbUo5sQ16aEk06YbySmZ0cQkFM9KMQeK+u+PHiPxpGcCpZcD6Erj7A9TMQTwNaJ8/8DcopGod8cVNfPFwRUZClv4zXBU19MNPb0mB5ccXhLdGpMVjTL7XIFQfhibzKV8LXCRlQaWdA4JP7Qjml5t/00syW1y1j1wllnYrhIvzOo+EyAbw/zpA552dntaJvvanfTF3aDF6X02v372xyaGjLoPGegK4TKhb7SUGtX0B7pqC36m64Gmt3xiMFpGPvpIbctxHGs73jeCr4G8jY2b5UmoN4UPvbEA+WDpOZTOCceN5Ku3hKUQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(376002)(136003)(346002)(39860400002)(46966006)(36840700001)(2906002)(6916009)(86362001)(36860700001)(70586007)(316002)(70206006)(6666004)(47076005)(8936002)(426003)(336012)(55016002)(8676002)(36756003)(478600001)(7696005)(5660300002)(26005)(16526019)(1076003)(2616005)(82310400003)(186003)(7636003)(356005)(82740400003)(6286002)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2021 14:22:16.0566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae3892d4-aa4c-42b9-a6e7-08d96ee63b17 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3969 Subject: [dpdk-dev] [PATCH 2/5] common/mlx5: update new MMO HCA capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" New MMO HCA capabilities were added and others were renamed. Align hca capabilities with new prm. Add support in devx interface for changes in HCA capabilities. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 11 ++++++++--- drivers/common/mlx5/mlx5_devx_cmds.h | 11 ++++++++--- drivers/common/mlx5/mlx5_prm.h | 20 ++++++++++++++------ 3 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index ac554cca05..fbc2123883 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -858,9 +858,14 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); attr->reg_c_preserve = MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); - attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); - attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); - attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); + attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); + attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); + attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); + attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, compress_mmo_sq); + attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, decompress_mmo_sq); + attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); + attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, compress_mmo_qp); + attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, decompress_mmo_qp); attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, compress_min_block_size); attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index c071629904..b21df0fd9b 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -173,9 +173,14 @@ struct mlx5_hca_attr { uint32_t log_max_srq; uint32_t log_max_srq_sz; uint32_t rss_ind_tbl_cap; - uint32_t mmo_dma_en:1; - uint32_t mmo_compress_en:1; - uint32_t mmo_decompress_en:1; + uint32_t mmo_dma_sq_en:1; + uint32_t mmo_compress_sq_en:1; + uint32_t mmo_decompress_sq_en:1; + uint32_t mmo_dma_qp_en:1; + uint32_t mmo_compress_qp_en:1; + uint32_t mmo_decompress_qp_en:1; + uint32_t mmo_regex_qp_en:1; + uint32_t mmo_regex_sq_en:1; uint32_t compress_min_block_size:4; uint32_t log_max_mmo_dma:5; uint32_t log_max_mmo_compress:5; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index d361bcf90e..070c538c8c 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1386,10 +1386,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 rtr2rts_qp_counters_set_id[0x1]; u8 rts2rts_udp_sport[0x1]; u8 rts2rts_lag_tx_port_affinity[0x1]; - u8 dma_mmo[0x1]; + u8 dma_mmo_sq[0x1]; u8 compress_min_block_size[0x4]; - u8 compress[0x1]; - u8 decompress[0x1]; + u8 compress_mmo_sq[0x1]; + u8 decompress_mmo_sq[0x1]; u8 log_max_ra_res_qp[0x6]; u8 end_pad[0x1]; u8 cc_query_allowed[0x1]; @@ -1519,7 +1519,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_lag_ports[0x4]; u8 reserved_at_280[0x10]; u8 max_wqe_sz_sq[0x10]; - u8 reserved_at_2a0[0x10]; + u8 reserved_at_2a0[0xe]; + u8 regexp_mmo_sq[0x1]; + u8 reserved_at_2b0[0x1]; u8 max_wqe_sz_rq[0x10]; u8 max_flow_counter_31_16[0x10]; u8 max_wqe_sz_sq_dc[0x10]; @@ -1632,7 +1634,12 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_vhca_ports[0x8]; u8 reserved_at_618[0x6]; u8 sw_owner_id[0x1]; - u8 reserved_at_61f[0x1e1]; + u8 reserved_at_61f[0x109]; + u8 dma_mmo_qp[0x1]; + u8 regexp_mmo_qp[0x1]; + u8 compress_mmo_qp[0x1]; + u8 decompress_mmo_qp[0x1]; + u8 reserved_at_624[0xd4]; }; struct mlx5_ifc_qos_cap_bits { @@ -3244,7 +3251,8 @@ struct mlx5_ifc_create_qp_in_bits { u8 uid[0x10]; u8 reserved_at_20[0x10]; u8 op_mod[0x10]; - u8 reserved_at_40[0x40]; + u8 qpc_ext[0x1]; + u8 reserved_at_41[0x3f]; u8 opt_param_mask[0x20]; u8 reserved_at_a0[0x20]; struct mlx5_ifc_qpc_bits qpc;