@@ -770,6 +770,7 @@ static int
test_dmadev_instance(uint16_t dev_id)
{
#define TEST_RINGSIZE 512
+ /* Setup of the dmadev device. 8< */
struct rte_dmadev_stats stats;
struct rte_dmadev_info info;
const struct rte_dmadev_conf conf = { .nb_vchans = 1};
@@ -795,7 +796,7 @@ test_dmadev_instance(uint16_t dev_id)
PRINT_ERR("Error with queue configuration\n");
return -1;
}
-
+ /* >8 End of setup of the dmadev device. */
rte_dmadev_info_get(dev_id, &info);
if (info.nb_vchans != 1) {
PRINT_ERR("Error, no configured queues reported on device id %u\n", dev_id);
@@ -120,3 +120,36 @@ use a subset of configured queues.
Once probed successfully, irrespective of kernel driver, the device will appear as a ``dmadev``,
that is a "DMA device type" inside DPDK, and can be accessed using APIs from the
``rte_dmadev`` library.
+
+Using IDXD DMAdev Devices
+--------------------------
+
+To use the devices from an application, the dmadev API can be used.
+
+Getting Device Information
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Basic information about each dmadev device can be queried using the
+``rte_dmadev_info_get()`` API. This will return basic device information such as
+the ``rte_device`` structure, device capabilities and other device specific values.
+
+Device Configuration
+~~~~~~~~~~~~~~~~~~~~~
+
+Configuring an IDXD dmadev device is done using the ``rte_dmadev_configure()`` and
+``rte_dmadev_vchan_setup`` APIs. The configurations are passed to these APIs using
+the ``rte_dmadev_conf`` and ``rte_dmadev_vchan_conf`` structures, respectively. For
+example, these can be used to configure the number of ``vchans`` per device, the
+ring size, etc. The ring size must be a power of two, between 64 and 4096.
+
+The following code shows how the device is configured in
+``test_dmadev.c``:
+
+.. literalinclude:: ../../../app/test/test_dmadev.c
+ :language: c
+ :start-after: Setup of the dmadev device. 8<
+ :end-before: >8 End of setup of the dmadev device.
+ :dedent: 1
+
+Once configured, the device can then be made ready for use by calling the
+``rte_dmadev_start()`` API.
@@ -95,6 +95,9 @@ idxd_dev_close(struct rte_dmadev *dev)
static const struct rte_dmadev_ops idxd_vdev_ops = {
.dev_close = idxd_dev_close,
.dev_dump = idxd_dump,
+ .dev_configure = idxd_configure,
+ .vchan_setup = idxd_vchan_setup,
+ .dev_info_get = idxd_info_get,
};
static void *
@@ -39,6 +39,72 @@ idxd_dump(const struct rte_dmadev *dev, FILE *f)
return 0;
}
+int
+idxd_info_get(const struct rte_dmadev *dev, struct rte_dmadev_info *info, uint32_t size)
+{
+ struct idxd_dmadev *idxd = dev->dev_private;
+
+ if (size < sizeof(*info))
+ return -EINVAL;
+
+ *info = (struct rte_dmadev_info) {
+ .device = dev->device,
+ .dev_capa = RTE_DMADEV_CAPA_MEM_TO_MEM |
+ RTE_DMADEV_CAPA_OPS_COPY | RTE_DMADEV_CAPA_OPS_FILL,
+ .max_vchans = 1,
+ .max_desc = 4096,
+ .min_desc = 64,
+ .nb_vchans = (idxd->desc_ring != NULL), /* returns 1 or 0 */
+ };
+ if (idxd->sva_support)
+ info->dev_capa |= RTE_DMADEV_CAPA_SVA;
+ return 0;
+}
+
+int
+idxd_configure(struct rte_dmadev *dev __rte_unused, const struct rte_dmadev_conf *dev_conf)
+{
+ if (dev_conf->nb_vchans != 1)
+ return -EINVAL;
+ return 0;
+}
+
+int
+idxd_vchan_setup(struct rte_dmadev *dev, uint16_t vchan __rte_unused,
+ const struct rte_dmadev_vchan_conf *qconf)
+{
+ struct idxd_dmadev *idxd = dev->dev_private;
+ uint16_t max_desc = qconf->nb_desc;
+
+ idxd->qcfg = *qconf;
+
+ if (!rte_is_power_of_2(max_desc))
+ max_desc = rte_align32pow2(max_desc);
+ IDXD_PMD_DEBUG("DMA dev %u using %u descriptors", dev->data->dev_id, max_desc);
+ idxd->desc_ring_mask = max_desc - 1;
+ idxd->qcfg.nb_desc = max_desc;
+
+ /* in case we are reconfiguring a device, free any existing memory */
+ rte_free(idxd->desc_ring);
+
+ /* allocate the descriptor ring at 2x size as batches can't wrap */
+ idxd->desc_ring = rte_zmalloc(NULL, sizeof(*idxd->desc_ring) * max_desc * 2, 0);
+ if (idxd->desc_ring == NULL)
+ return -ENOMEM;
+ idxd->desc_iova = rte_mem_virt2iova(idxd->desc_ring);
+
+ idxd->batch_idx_read = 0;
+ idxd->batch_idx_write = 0;
+ idxd->batch_start = 0;
+ idxd->batch_size = 0;
+ idxd->ids_returned = 0;
+ idxd->ids_avail = 0;
+
+ memset(idxd->batch_comp_ring, 0, sizeof(*idxd->batch_comp_ring) *
+ (idxd->max_batches + 1));
+ return 0;
+}
+
int
idxd_dmadev_create(const char *name, struct rte_device *dev,
const struct idxd_dmadev *base_idxd,
@@ -80,5 +80,10 @@ struct idxd_dmadev {
int idxd_dmadev_create(const char *name, struct rte_device *dev,
const struct idxd_dmadev *base_idxd, const struct rte_dmadev_ops *ops);
int idxd_dump(const struct rte_dmadev *dev, FILE *f);
+int idxd_configure(struct rte_dmadev *dev, const struct rte_dmadev_conf *dev_conf);
+int idxd_vchan_setup(struct rte_dmadev *dev, uint16_t vchan,
+ const struct rte_dmadev_vchan_conf *qconf);
+int idxd_info_get(const struct rte_dmadev *dev, struct rte_dmadev_info *dev_info,
+ uint32_t size);
#endif /* _IDXD_INTERNAL_H_ */
@@ -61,6 +61,9 @@ idxd_is_wq_enabled(struct idxd_dmadev *idxd)
static const struct rte_dmadev_ops idxd_pci_ops = {
.dev_dump = idxd_dump,
+ .dev_configure = idxd_configure,
+ .vchan_setup = idxd_vchan_setup,
+ .dev_info_get = idxd_info_get,
};
/* each portal uses 4 x 4k pages */