From patchwork Thu Sep 2 07:00:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 97761 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FC0FA0547; Thu, 2 Sep 2021 09:00:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A3D3340DDE; Thu, 2 Sep 2021 09:00:52 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 76F6E40142 for ; Thu, 2 Sep 2021 09:00:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1823lgrH027710; Thu, 2 Sep 2021 00:00:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=edI1ULTNqzsAEtAG8EyY0TSiuTDi/E3MRXq4mfaj7N4=; b=Nt2HtPjzTRwlUILNGQPdvcQJQnNeamisUuv7XAQjyUK/2BnlqqsNt33KzQcqDEDXhZTB 5oOCPqhxeUCWa9gUWBanS4BrujjMkTFH2t1j+Luh9/AnOrGuMoTAII88VWHjZe2KdF2S 5jqDYCWAy6KbqplUYGUEAXIEfXG9EZeZSzzLKckRR5Ok5kPHRAYtk1wZHq2foEERXzIP UH4hh9q5MtODx5z8JqfmSaCqHUTjGwukj2EKnH/Dl2UPb2Moo55tev8gQGoV1roMx6w3 pEQcX8kieBRSftlhJUEs7wuDjqP1JhkGIUy0J97Te9cGDOiip+s1R0k2nLGf21KJrC7x 8w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3atdwqae6g-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 02 Sep 2021 00:00:46 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 2 Sep 2021 00:00:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 2 Sep 2021 00:00:44 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 525D23F7051; Thu, 2 Sep 2021 00:00:42 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Pavan Nikhilesh Date: Thu, 2 Sep 2021 12:30:32 +0530 Message-ID: <20210902070034.1086-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: LZTp_Ov-dCvo5VGNmQfa3IEqovbrNCl3 X-Proofpoint-GUID: LZTp_Ov-dCvo5VGNmQfa3IEqovbrNCl3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-02_02,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 1/2] common/cnxk: add SSO XAQ pool create and free X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add common API to create and free SSO XAQ pool. Signed-off-by: Pavan Nikhilesh --- Depends-on: series-18612 ("net/cnxk: support for inline ipsec") drivers/common/cnxk/roc_sso.c | 122 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_sso.h | 14 ++++ drivers/common/cnxk/roc_sso_priv.h | 5 ++ drivers/common/cnxk/version.map | 2 + 4 files changed, 143 insertions(+) -- 2.32.0 diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index bdf973fc2a..31cae30c88 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -5,6 +5,8 @@ #include "roc_api.h" #include "roc_priv.h" +#define SSO_XAQ_CACHE_CNT (0x7) + /* Private functions. */ int sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf, @@ -387,6 +389,126 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos, return mbox_process(dev->mbox); } +int +sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint32_t nb_xae, uint32_t xae_waes, + uint32_t xaq_buf_size, uint16_t nb_hwgrp) +{ + struct npa_pool_s pool; + struct npa_aura_s aura; + plt_iova_t iova; + uint32_t i; + int rc; + + if (xaq->mem != NULL) { + rc = sso_hwgrp_release_xaq(dev, nb_hwgrp); + if (rc < 0) { + plt_err("Failed to release XAQ %d", rc); + return rc; + } + roc_npa_pool_destroy(xaq->aura_handle); + plt_free(xaq->fc); + plt_free(xaq->mem); + memset(xaq, 0, sizeof(struct roc_sso_xaq_data)); + } + + xaq->fc = plt_zmalloc(ROC_ALIGN, ROC_ALIGN); + if (xaq->fc == NULL) { + plt_err("Failed to allocate XAQ FC"); + rc = -ENOMEM; + goto fail; + } + + /* Taken from HRM 14.3.3(4) */ + nb_xae += (xae_waes * SSO_XAQ_CACHE_CNT * nb_hwgrp); + xaq->nb_xae = nb_xae; + xaq->nb_xaq = xaq->nb_xae / xae_waes; + + xaq->mem = plt_zmalloc(xaq_buf_size * xaq->nb_xaq, xaq_buf_size); + if (xaq->mem == NULL) { + plt_err("Failed to allocate XAQ mem"); + rc = -ENOMEM; + goto free_fc; + } + + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + aura.fc_ena = 1; + aura.fc_addr = (uint64_t)xaq->fc; + aura.fc_hyst_bits = 0; /* Store count on all updates */ + rc = roc_npa_pool_create(&xaq->aura_handle, xaq_buf_size, xaq->nb_xaq, + &aura, &pool); + if (rc) { + plt_err("Failed to create XAQ pool"); + goto npa_fail; + } + + iova = (uint64_t)xaq->mem; + for (i = 0; i < xaq->nb_xaq; i++) { + roc_npa_aura_op_free(xaq->aura_handle, 0, iova); + iova += xaq_buf_size; + } + roc_npa_aura_op_range_set(xaq->aura_handle, (uint64_t)xaq->mem, iova); + + /* When SW does addwork (enqueue) check if there is space in XAQ by + * comparing fc_addr above against the xaq_lmt calculated below. + * There should be a minimum headroom of one XAQ per HWGRP for SSO + * to request XAQ to cache them even before enqueue is called. + */ + xaq->xaq_lmt = xaq->nb_xaq - nb_hwgrp; + return 0; +npa_fail: + plt_free(xaq->mem); +free_fc: + plt_free(xaq->fc); +fail: + memset(xaq, 0, sizeof(struct roc_sso_xaq_data)); + return rc; +} + +int +roc_sso_hwgrp_init_xaq_aura(struct roc_sso *roc_sso, uint32_t nb_xae) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return sso_hwgrp_init_xaq_aura(dev, &roc_sso->xaq, nb_xae, + roc_sso->xae_waes, roc_sso->xaq_buf_size, + roc_sso->nb_hwgrp); +} + +int +sso_hwgrp_free_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint16_t nb_hwgrp) +{ + int rc; + + if (xaq->mem != NULL) { + if (nb_hwgrp) { + rc = sso_hwgrp_release_xaq(dev, nb_hwgrp); + if (rc < 0) { + plt_err("Failed to release XAQ %d", rc); + return rc; + } + } + roc_npa_pool_destroy(xaq->aura_handle); + plt_free(xaq->fc); + plt_free(xaq->mem); + } + memset(xaq, 0, sizeof(struct roc_sso_xaq_data)); + + return 0; +} + +int +roc_sso_hwgrp_free_xaq_aura(struct roc_sso *roc_sso, uint16_t nb_hwgrp) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return sso_hwgrp_free_xaq_aura(dev, &roc_sso->xaq, nb_hwgrp); +} + int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps) { diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index b28f6089cc..27d49c6c68 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -27,6 +27,15 @@ struct roc_sso_hwgrp_stats { uint64_t page_cnt; }; +struct roc_sso_xaq_data { + uint32_t nb_xaq; + uint32_t nb_xae; + uint32_t xaq_lmt; + uint64_t aura_handle; + void *fc; + void *mem; +}; + struct roc_sso { struct plt_pci_device *pci_dev; /* Public data. */ @@ -35,6 +44,7 @@ struct roc_sso { uint16_t nb_hwgrp; uint8_t nb_hws; uintptr_t lmt_base; + struct roc_sso_xaq_data xaq; /* HW Const. */ uint32_t xae_waes; uint32_t xaq_buf_size; @@ -95,6 +105,10 @@ int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws); uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp); +int __roc_api roc_sso_hwgrp_init_xaq_aura(struct roc_sso *roc_sso, + uint32_t nb_xae); +int __roc_api roc_sso_hwgrp_free_xaq_aura(struct roc_sso *roc_sso, + uint16_t nb_hwgrp); /* Debug */ void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws, diff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h index 8dffa3fbf4..2e1b025d1c 100644 --- a/drivers/common/cnxk/roc_sso_priv.h +++ b/drivers/common/cnxk/roc_sso_priv.h @@ -47,6 +47,11 @@ void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, uint16_t hwgrp[], uint16_t n, uint16_t enable); int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps); int sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps); +int sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint32_t nb_xae, uint32_t xae_waes, + uint32_t xaq_buf_size, uint16_t nb_hwgrp); +int sso_hwgrp_free_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, + uint16_t nb_hwgrp); /* SSO IRQ */ int sso_register_irqs_priv(struct roc_sso *roc_sso, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 9fcc677e34..153c45b910 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -280,7 +280,9 @@ INTERNAL { roc_sso_dump; roc_sso_hwgrp_alloc_xaq; roc_sso_hwgrp_base_get; + roc_sso_hwgrp_free_xaq_aura; roc_sso_hwgrp_hws_link_status; + roc_sso_hwgrp_init_xaq_aura; roc_sso_hwgrp_qos_config; roc_sso_hwgrp_release_xaq; roc_sso_hwgrp_set_priority;