diff mbox series

common/cnxk: align npa stack to roc cache line size

Message ID 20210830135231.2610152-1-asekhar@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Jerin Jacob
Headers
Series common/cnxk: align npa stack to roc cache line size |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/github-robot: build success github build: passed
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-mellanox-Performance fail Performance Testing issues
ci/iol-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-aarch64-unit-testing fail Testing issues

Commit Message

Ashwin Sekhar T K Aug. 30, 2021, 1:52 p.m. UTC 
  NPA stack should be aligned to ROC cache line size.

Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
 drivers/common/cnxk/roc_npa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jerin Jacob Sept. 16, 2021, 2:27 p.m. UTC | #1 
On Mon, Aug 30, 2021 at 7:23 PM Ashwin Sekhar T K <asekhar@marvell.com> wrote:
>
> NPA stack should be aligned to ROC cache line size.
>
> Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
>
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>


Acked-by: Jerin Jacob <jerinj@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks

> ---
>  drivers/common/cnxk/roc_npa.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> index d064d125c1..a0d2cc8f19 100644
> --- a/drivers/common/cnxk/roc_npa.c
> +++ b/drivers/common/cnxk/roc_npa.c
> @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
>  {
>         const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
>
> -       return plt_memzone_reserve_cache_align(mz_name, size);
> +       return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
>  }
>
>  static inline int
> --
> 2.32.0
>
Ferruh Yigit Sept. 16, 2021, 3:15 p.m. UTC | #2 
On 8/30/2021 2:52 PM, Ashwin Sekhar T K wrote:
> NPA stack should be aligned to ROC cache line size.
> 

Can you please document the long versions of 'NPA' & 'ROC' abbreviations?

Also for the patch title, since abbreviations needs to be uppercase, to automate
the check for these abbreviations, can you please add them to
'./devtools/words-case.txt' in separate patch.

And can you add some more context on the reasoning of the change, why it should
be aligned to cache line?
What is the impact user/application sees if it is not aligned, and after aligned?

Thanks,
ferruh

> Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
> 
> Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
> ---
>  drivers/common/cnxk/roc_npa.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> index d064d125c1..a0d2cc8f19 100644
> --- a/drivers/common/cnxk/roc_npa.c
> +++ b/drivers/common/cnxk/roc_npa.c
> @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
>  {
>  	const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
>  
> -	return plt_memzone_reserve_cache_align(mz_name, size);
> +	return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
>  }
>  
>  static inline int
>
Jerin Jacob Sept. 16, 2021, 4:35 p.m. UTC | #3 
On Thu, Sep 16, 2021 at 8:46 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 8/30/2021 2:52 PM, Ashwin Sekhar T K wrote:
> > NPA stack should be aligned to ROC cache line size.
> >
>
> Can you please document the long versions of 'NPA' & 'ROC' abbreviations?
>
> Also for the patch title, since abbreviations needs to be uppercase, to automate
> the check for these abbreviations, can you please add them to
> './devtools/words-case.txt' in separate patch.

Please do add  NIX, NPC, CPT, SSO, LBK, MCAM too.


> And can you add some more context on the reasoning of the change, why it should
> be aligned to cache line?
> What is the impact user/application sees if it is not aligned, and after aligned?
>
> Thanks,
> ferruh
>
> > Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
> >
> > Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
> > ---
> >  drivers/common/cnxk/roc_npa.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> > index d064d125c1..a0d2cc8f19 100644
> > --- a/drivers/common/cnxk/roc_npa.c
> > +++ b/drivers/common/cnxk/roc_npa.c
> > @@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
> >  {
> >       const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
> >
> > -     return plt_memzone_reserve_cache_align(mz_name, size);
> > +     return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
> >  }
> >
> >  static inline int
> >
>
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index d064d125c1..a0d2cc8f19 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -194,7 +194,7 @@  npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
 {
 	const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
 
-	return plt_memzone_reserve_cache_align(mz_name, size);
+	return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
 }
 
 static inline int