From patchwork Mon Aug 2 10:18:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 96524 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1DE3CA0C41; Mon, 2 Aug 2021 12:20:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 084AB4114D; Mon, 2 Aug 2021 12:20:53 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id D0BE241136 for ; Mon, 2 Aug 2021 12:20:51 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6620AD6E; Mon, 2 Aug 2021 03:20:51 -0700 (PDT) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.222]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AE3413F70D; Mon, 2 Aug 2021 03:20:44 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, ruifeng.wang@arm.com, konstantin.ananyev@intel.com, rsanford@akamai.com, erik.g.carrillo@intel.com, olivier.matz@6wind.com, yipeng1.wang@intel.com, sameh.gobriel@intel.com, bruce.richardson@intel.com, vladimir.medvedkin@intel.com, anatoly.burakov@intel.com, andrew.rybchenko@oktetlabs.ru, jerinj@marvell.com, declan.doherty@intel.com, ciara.power@intel.com, xiaoyun.li@intel.com, nicolas.chautru@intel.com, maryam.tahhan@intel.com, reshma.pattan@intel.com, cristian.dumitrescu@intel.com Cc: dev@dpdk.org, nd@arm.com Date: Mon, 2 Aug 2021 05:18:43 -0500 Message-Id: <20210802101847.3462-9-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210802101847.3462-1-joyce.kong@arm.com> References: <20210802101847.3462-1-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v1 08/12] app/crypto: use compiler atomic builtins for display sync X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Covert rte_atomic_test_and_set usage to compiler atomic CAS operation for display sync in crypto cases. Signed-off-by: Joyce Kong Reviewed-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli --- app/test-crypto-perf/cperf_test_latency.c | 6 ++++-- app/test-crypto-perf/cperf_test_pmd_cyclecount.c | 9 ++++++--- app/test-crypto-perf/cperf_test_throughput.c | 9 ++++++--- app/test-crypto-perf/cperf_test_verify.c | 9 ++++++--- 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/app/test-crypto-perf/cperf_test_latency.c b/app/test-crypto-perf/cperf_test_latency.c index 159fe8492b..5e73c75fba 100644 --- a/app/test-crypto-perf/cperf_test_latency.c +++ b/app/test-crypto-perf/cperf_test_latency.c @@ -126,7 +126,7 @@ cperf_latency_test_runner(void *arg) uint8_t burst_size_idx = 0; uint32_t imix_idx = 0; - static rte_atomic16_t display_once = RTE_ATOMIC16_INIT(0); + static uint16_t display_once; if (ctx == NULL) return 0; @@ -308,7 +308,9 @@ cperf_latency_test_runner(void *arg) time_min = tunit*(double)(tsc_min) / tsc_hz; if (ctx->options->csv) { - if (rte_atomic16_test_and_set(&display_once)) + uint16_t exp = 0; + if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) printf("\n# lcore, Buffer Size, Burst Size, Pakt Seq #, " "cycles, time (us)"); diff --git a/app/test-crypto-perf/cperf_test_pmd_cyclecount.c b/app/test-crypto-perf/cperf_test_pmd_cyclecount.c index 844659aeca..a1de334efb 100644 --- a/app/test-crypto-perf/cperf_test_pmd_cyclecount.c +++ b/app/test-crypto-perf/cperf_test_pmd_cyclecount.c @@ -404,7 +404,7 @@ cperf_pmd_cyclecount_test_runner(void *test_ctx) state.lcore = rte_lcore_id(); state.linearize = 0; - static rte_atomic16_t display_once = RTE_ATOMIC16_INIT(0); + static uint16_t display_once; static bool warmup = true; /* @@ -449,8 +449,10 @@ cperf_pmd_cyclecount_test_runner(void *test_ctx) continue; } + uint16_t exp = 0; if (!opts->csv) { - if (rte_atomic16_test_and_set(&display_once)) + if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) printf(PRETTY_HDR_FMT, "lcore id", "Buf Size", "Burst Size", "Enqueued", "Dequeued", "Enq Retries", @@ -466,7 +468,8 @@ cperf_pmd_cyclecount_test_runner(void *test_ctx) state.cycles_per_enq, state.cycles_per_deq); } else { - if (rte_atomic16_test_and_set(&display_once)) + if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) printf(CSV_HDR_FMT, "# lcore id", "Buf Size", "Burst Size", "Enqueued", "Dequeued", "Enq Retries", diff --git a/app/test-crypto-perf/cperf_test_throughput.c b/app/test-crypto-perf/cperf_test_throughput.c index f6eb8cf259..1407007c6e 100644 --- a/app/test-crypto-perf/cperf_test_throughput.c +++ b/app/test-crypto-perf/cperf_test_throughput.c @@ -106,7 +106,7 @@ cperf_throughput_test_runner(void *test_ctx) uint8_t burst_size_idx = 0; uint32_t imix_idx = 0; - static rte_atomic16_t display_once = RTE_ATOMIC16_INIT(0); + static uint16_t display_once; struct rte_crypto_op *ops[ctx->options->max_burst_size]; struct rte_crypto_op *ops_processed[ctx->options->max_burst_size]; @@ -272,8 +272,10 @@ cperf_throughput_test_runner(void *test_ctx) double cycles_per_packet = ((double)tsc_duration / ctx->options->total_ops); + uint16_t exp = 0; if (!ctx->options->csv) { - if (rte_atomic16_test_and_set(&display_once)) + if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) printf("%12s%12s%12s%12s%12s%12s%12s%12s%12s%12s\n\n", "lcore id", "Buf Size", "Burst Size", "Enqueued", "Dequeued", "Failed Enq", @@ -293,7 +295,8 @@ cperf_throughput_test_runner(void *test_ctx) throughput_gbps, cycles_per_packet); } else { - if (rte_atomic16_test_and_set(&display_once)) + if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) printf("#lcore id,Buffer Size(B)," "Burst Size,Enqueued,Dequeued,Failed Enq," "Failed Deq,Ops(Millions),Throughput(Gbps)," diff --git a/app/test-crypto-perf/cperf_test_verify.c b/app/test-crypto-perf/cperf_test_verify.c index 2939aeaa93..0c053ad3c0 100644 --- a/app/test-crypto-perf/cperf_test_verify.c +++ b/app/test-crypto-perf/cperf_test_verify.c @@ -241,7 +241,7 @@ cperf_verify_test_runner(void *test_ctx) uint64_t ops_deqd = 0, ops_deqd_total = 0, ops_deqd_failed = 0; uint64_t ops_failed = 0; - static rte_atomic16_t display_once = RTE_ATOMIC16_INIT(0); + static uint16_t display_once; uint64_t i; uint16_t ops_unused = 0; @@ -383,8 +383,10 @@ cperf_verify_test_runner(void *test_ctx) ops_deqd_total += ops_deqd; } + uint16_t exp = 0; if (!ctx->options->csv) { - if (rte_atomic16_test_and_set(&display_once)) + if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) printf("%12s%12s%12s%12s%12s%12s%12s%12s\n\n", "lcore id", "Buf Size", "Burst size", "Enqueued", "Dequeued", "Failed Enq", @@ -401,7 +403,8 @@ cperf_verify_test_runner(void *test_ctx) ops_deqd_failed, ops_failed); } else { - if (rte_atomic16_test_and_set(&display_once)) + if (__atomic_compare_exchange_n(&display_once, &exp, 1, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) printf("\n# lcore id, Buffer Size(B), " "Burst Size,Enqueued,Dequeued,Failed Enq," "Failed Deq,Failed Ops\n");