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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 16:42:18.2700 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83bd2239-0260-46f8-c537-08d947af8285 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3181 Subject: [dpdk-dev] [PATCH v8 09/16] crypto/mlx5: add keytag devarg X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Suanming Mou A keytag is a piece of data encrypted together with a DEK. When a DEK is referenced by an MKEY.bsf through its index, the keytag is also supplied in the BSF as plaintext. The HW will decrypt the DEK (and the attached keytag) and will fail the operation if the keytags don't match. This commit adds the configuration of the keytag with devargs. Signed-off-by: Suanming Mou Signed-off-by: Matan Azrad --- doc/guides/cryptodevs/mlx5.rst | 7 +++++ drivers/crypto/mlx5/mlx5_crypto.c | 50 +++++++++++++++++-------------- drivers/crypto/mlx5/mlx5_crypto.h | 3 +- 3 files changed, 37 insertions(+), 23 deletions(-) diff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst index 6cae5affbd..c3632484a5 100644 --- a/doc/guides/cryptodevs/mlx5.rst +++ b/doc/guides/cryptodevs/mlx5.rst @@ -52,6 +52,9 @@ wrapping. The credential and the AES-XTS keys should be provided to the hardware, as ciphertext encrypted by the KEK. +A keytag (64 bits) should be appended to the AES-XTS keys (before wrapping), +and will be validated when the hardware attempts to access it. + When crypto engines are defined to work in wrapped import method, they come out of the factory in Commissioning mode, and thus, cannot be used for crypto operations yet. A dedicated tool is used for changing the mode from Commissioning to @@ -113,6 +116,10 @@ Driver options The identifier of the credential, default value is 0 represents the operational register credential. +- ``keytag`` parameter [int] + + The plaintext of the keytag appanded to the AES-XTS keys, default value is 0. + Supported NICs -------------- diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index cbaa2e52ff..0f786ac4ca 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -500,56 +500,52 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque) attr->session_import_kek_ptr = (uint32_t)tmp; else if (strcmp(key, "credential_id") == 0) attr->credential_pointer = (uint32_t)tmp; + else if (strcmp(key, "keytag") == 0) + devarg_prms->keytag = tmp; else DRV_LOG(WARNING, "Invalid key %s.", key); return 0; } -static struct mlx5_devx_obj * -mlx5_crypto_config_login(struct rte_devargs *devargs, - struct ibv_context *ctx) +static int +mlx5_crypto_parse_devargs(struct rte_devargs *devargs, + struct mlx5_crypto_devarg_params *devarg_prms) { - /* - * Set credential pointer and session import KEK pointer to a default - * value of 0. - */ - struct mlx5_crypto_devarg_params login = { - .login_devarg = false, - .login_attr = { - .credential_pointer = 0, - .session_import_kek_ptr = 0, - } - }; + struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr; struct rte_kvargs *kvlist; + /* Default values. */ + attr->credential_pointer = 0; + attr->session_import_kek_ptr = 0; + devarg_prms->keytag = 0; if (devargs == NULL) { DRV_LOG(ERR, "No login devargs in order to enable crypto operations in the device."); rte_errno = EINVAL; - return NULL; + return -1; } kvlist = rte_kvargs_parse(devargs->args, NULL); if (kvlist == NULL) { DRV_LOG(ERR, "Failed to parse devargs."); rte_errno = EINVAL; - return NULL; + return -1; } if (rte_kvargs_process(kvlist, NULL, mlx5_crypto_args_check_handler, - &login) != 0) { + devarg_prms) != 0) { DRV_LOG(ERR, "Devargs handler function Failed."); rte_kvargs_free(kvlist); rte_errno = EINVAL; - return NULL; + return -1; } rte_kvargs_free(kvlist); - if (login.login_devarg == false) { + if (devarg_prms->login_devarg == false) { DRV_LOG(ERR, "No login credential devarg in order to enable crypto operations " "in the device."); rte_errno = EINVAL; - return NULL; + return -1; } - return mlx5_devx_cmd_create_crypto_login_obj(ctx, &login.login_attr); + return 0; } /** @@ -609,6 +605,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, struct ibv_context *ctx; struct mlx5_devx_obj *login; struct mlx5_crypto_priv *priv; + struct mlx5_crypto_devarg_params devarg_prms = { 0 }; struct mlx5_hca_attr attr = { 0 }; struct rte_cryptodev_pmd_init_params init_params = { .name = "", @@ -617,6 +614,8 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, .max_nb_queue_pairs = RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS, }; + int ret; + RTE_SET_USED(pci_drv); if (rte_eal_process_type() != RTE_PROC_PRIMARY) { DRV_LOG(ERR, "Non-primary process type is not supported."); @@ -646,7 +645,13 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, rte_errno = ENOTSUP; return -ENOTSUP; } - login = mlx5_crypto_config_login(pci_dev->device.devargs, ctx); + ret = mlx5_crypto_parse_devargs(pci_dev->device.devargs, &devarg_prms); + if (ret) { + DRV_LOG(ERR, "Failed to parse devargs."); + return -rte_errno; + } + login = mlx5_devx_cmd_create_crypto_login_obj(ctx, + &devarg_prms.login_attr); if (login == NULL) { DRV_LOG(ERR, "Failed to configure login."); return -rte_errno; @@ -686,6 +691,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, } priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; + priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); /* Register callback function for global shared MR cache management. */ if (TAILQ_EMPTY(&mlx5_crypto_priv_list)) rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index b98c621c23..d374d3c4e9 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -30,6 +30,7 @@ struct mlx5_crypto_priv { struct rte_cryptodev_config dev_config; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ struct mlx5_devx_obj *login_obj; + uint64_t keytag; }; struct mlx5_crypto_qp { @@ -49,10 +50,10 @@ struct mlx5_crypto_dek { bool size_is_48; /* Whether the key\data size is 48 bytes or not. */ } __rte_cache_aligned; - struct mlx5_crypto_devarg_params { bool login_devarg; struct mlx5_devx_crypto_login_attr login_attr; + uint64_t keytag; }; int