| Message ID | 20210713125442.1366424-1-lmargalit@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Raslan Darawsheh |
| Headers | show |
| Series | [v1] net/mlx5: fix RSS selection flags settings | expand |
| Context | Check | Description |
|---|---|---|
| ci/iol-intel-Performance | fail | Performance Testing issues |
| ci/iol-testing | fail | Testing issues |
| ci/intel-Testing | success | Testing PASS |
| ci/Intel-compilation | success | Compilation OK |
| ci/iol-intel-Functional | success | Functional Testing PASS |
| ci/iol-abi-testing | success | Testing PASS |
| ci/github-robot | success | github build: passed |
| ci/checkpatch | success | coding style OK |
Hi, > -----Original Message----- > From: dev <dev-bounces@dpdk.org> On Behalf Of Lior Margalit > Sent: Tuesday, July 13, 2021 3:55 PM > To: dev@dpdk.org; Matan Azrad <matan@nvidia.com> > Cc: Lior Margalit <lmargalit@nvidia.com>; stable@dpdk.org > Subject: [dpdk-dev] [PATCH v1] net/mlx5: fix RSS selection flags settings > > The L3 protocol of the RSS type may be different than the one > defined in the flow. > If the RSS type also includes L4 protocol type, the selection > flags for the RX hash will be set with SPORT/DPORT without > setting SRC/DST IP, but this combination is not supported by > the rte API. > > When using indirect RSS action, the flow creation fails, > because it does not match any of the pre-created TIRs. > > The fix is to prevent setting the hash flags with SPORT/DPORT > without setting SRC/DST IP. The hash flags will remain 0, > meaning non-RSS processing of the received packets. > In case of indirect rss action, it will match the MLX5_RSS_HASH_NONE > pre-created TIR. > In addition, the queue_num is set to 1 when the hash flags are 0, > but it was implemented only when creating a new TIR. Applied the same > to the RSS desc before checking if it matches a cached TIR object. > > Fixes: b1d63d829378 ("net/mlx5: support RSS on src or dst fields only") > Fixes: 5a959cbfa68c ("net/mlx5: share Rx hash queue code") > Cc: stable@dpdk.org > > Signed-off-by: Lior Margalit <lmargalit@nvidia.com> > Acked-by: Matan Azrad <matan@nvidia.com> Patch applied to next-net-mlx, Kindest regards, Raslan Darawsheh
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 2f4c0eeb5b..99836b1796 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -10506,10 +10506,8 @@ flow_dv_hashfields_set(struct mlx5_flow *dev_flow, dev_flow->hash_fields = 0; #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT - if (rss_desc->level >= 2) { - dev_flow->hash_fields |= IBV_RX_HASH_INNER; + if (rss_desc->level >= 2) rss_inner = 1; - } #endif if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) || (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) { @@ -10532,6 +10530,12 @@ flow_dv_hashfields_set(struct mlx5_flow *dev_flow, dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH; } } + if (dev_flow->hash_fields == 0) + /* + * There is no match between the rss types and the + * l3 protocol (IPv4/IPv6) defined in the flow. + */ + return; if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) || (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) { if (rss_types & ETH_RSS_UDP) { @@ -10557,6 +10561,8 @@ flow_dv_hashfields_set(struct mlx5_flow *dev_flow, dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH; } } + if (rss_inner) + dev_flow->hash_fields |= IBV_RX_HASH_INNER; } /** @@ -10589,6 +10595,8 @@ flow_dv_hrxq_prepare(struct rte_eth_dev *dev, rss_desc->hash_fields = dev_flow->hash_fields; rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL); rss_desc->shared_rss = 0; + if (rss_desc->hash_fields == 0) + rss_desc->queue_num = 1; *hrxq_idx = mlx5_hrxq_get(dev, rss_desc); if (!*hrxq_idx) return NULL; diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index fe9673310a..527dcfbf26 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -1820,8 +1820,9 @@ flow_verbs_translate(struct rte_eth_dev *dev, flow_verbs_translate_item_tcp(dev_flow, items, item_flags); subpriority = MLX5_PRIORITY_MAP_L4; - dev_flow->hash_fields |= - mlx5_flow_hashfields_adjust + if (dev_flow->hash_fields != 0) + dev_flow->hash_fields |= + mlx5_flow_hashfields_adjust (rss_desc, tunnel, ETH_RSS_TCP, (IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP)); @@ -1832,8 +1833,9 @@ flow_verbs_translate(struct rte_eth_dev *dev, flow_verbs_translate_item_udp(dev_flow, items, item_flags); subpriority = MLX5_PRIORITY_MAP_L4; - dev_flow->hash_fields |= - mlx5_flow_hashfields_adjust + if (dev_flow->hash_fields != 0) + dev_flow->hash_fields |= + mlx5_flow_hashfields_adjust (rss_desc, tunnel, ETH_RSS_UDP, (IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP));
The L3 protocol of the RSS type may be different than the one defined in the flow. If the RSS type also includes L4 protocol type, the selection flags for the RX hash will be set with SPORT/DPORT without setting SRC/DST IP, but this combination is not supported by the rte API. When using indirect RSS action, the flow creation fails, because it does not match any of the pre-created TIRs. The fix is to prevent setting the hash flags with SPORT/DPORT without setting SRC/DST IP. The hash flags will remain 0, meaning non-RSS processing of the received packets. In case of indirect rss action, it will match the MLX5_RSS_HASH_NONE pre-created TIR. In addition, the queue_num is set to 1 when the hash flags are 0, but it was implemented only when creating a new TIR. Applied the same to the RSS desc before checking if it matches a cached TIR object. Fixes: b1d63d829378 ("net/mlx5: support RSS on src or dst fields only") Fixes: 5a959cbfa68c ("net/mlx5: share Rx hash queue code") Cc: stable@dpdk.org Signed-off-by: Lior Margalit <lmargalit@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com> --- drivers/net/mlx5/mlx5_flow_dv.c | 14 +++++++++++--- drivers/net/mlx5/mlx5_flow_verbs.c | 10 ++++++---- 2 files changed, 17 insertions(+), 7 deletions(-)